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263 lines
6.6 KiB
263 lines
6.6 KiB
/**
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*** Copyright (C) 1996-99 Intel Corporation. All rights reserved.
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***
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*** The information and source code contained herein is the exclusive
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*** property of Intel Corporation and may not be disclosed, examined
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*** or reproduced in whole or in part without explicit written authorization
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*** from the company.
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**/
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#if defined(__assembler)
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//
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// Define standard integer registers.
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//
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zero = r0 // always 0
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gp = r1 // global pointer
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v0 = r8 // return value
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sp = r12 // stack pointer
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s0 = r4 // saved (preserved) integer registers
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s1 = r5
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s2 = r6
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s3 = r7
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//
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// temporary (volatile) integer registers
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//
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t0 = r2
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t1 = r3
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t2 = r9
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t3 = r10
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t4 = r11
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t5 = r14
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t6 = r15
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t7 = r16
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t8 = r17
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t9 = r18
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t10 = r19
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t11 = r20
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t12 = r21
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t13 = r22
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t14 = r23
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t15 = r24
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t16 = r25
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t17 = r26
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t18 = r27
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t19 = r28
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t20 = r29
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t21 = r30
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t22 = r31
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//
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// Floating point saved (preserved) registers
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//
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fs0 = f2
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fs1 = f3
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fs2 = f4
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fs3 = f5
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fs4 = f16
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fs5 = f17
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fs6 = f18
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fs7 = f19
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fs8 = f20
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fs9 = f21
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fs10 = f22
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fs11 = f23
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fs12 = f24
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fs13 = f25
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fs14 = f26
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fs15 = f27
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fs16 = f28
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fs17 = f29
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fs18 = f30
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fs19 = f31
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//
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// Low floating point temporary (volatile) registers
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//
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ft0 = f6
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ft1 = f7
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ft2 = f8
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ft3 = f9
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ft4 = f10
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ft5 = f11
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ft6 = f12
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ft7 = f13
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ft8 = f14
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ft9 = f15
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//
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// input arguments
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// Should be:
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// a0 = in0
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// a1 = in1
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// a2 = in2
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// a3 = in3
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// a4 = in4
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// a5 = in5
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// a6 = in6
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// a7 = in7
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//
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a0 = r32
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a1 = r33
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a2 = r34
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a3 = r35
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a4 = r36
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a5 = r37
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a6 = r38
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a7 = r39
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//
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// branch return pointer (b0)
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//
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brp = rp
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//
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// branch saved (preserved)
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//
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bs0 = b1
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bs1 = b2
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bs2 = b3
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bs3 = b4
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bs4 = b5
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//
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// branch temporary (volatile) registers
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//
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bt0 = b6
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bt1 = b7
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//
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// predicate registers
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//
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// p0 predicate register always 1
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//
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ps0 = p1 // saved (preserved) predicate registers
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ps1 = p2
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ps2 = p3
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ps3 = p4
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ps4 = p5
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ps5 = p16 // Predicates p16-p63 are also preserved
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ps6 = p17
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ps7 = p18
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ps8 = p19
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ps9 = p20
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pt0 = p6 // temporary (volatile) predicate registers
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pt1 = p7
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pt2 = p8
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pt3 = p9
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pt4 = p10
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pt5 = p11
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pt6 = p12
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pt7 = p13
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pt8 = p14
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pt9 = p15
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//
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// Kernel registers
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//
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k0 = ar.k0
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k1 = ar.k1
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k2 = ar.k2
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k3 = ar.k3
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k4 = ar.k4
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k5 = ar.k5
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k6 = ar.k6
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k7 = ar.k7
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ia32dr67 = ar.k5 // dr6/dr7 for iA32
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ia32fcr = ar21 // FCR for iA32
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ia32eflag = ar24 // EFLAG for iA32
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ia32csd = ar25 // CSD for iA32
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ia32ssd = ar26 // SSD for iA32
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ia32cflag = ar27 // CFLG (cr0/cr4) for iA32
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ia32fsr = ar28 // FSR for iA32
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ia32fir = ar29 // FIR for iA32
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ia32fdr = ar30 // FDR for iA32
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//
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// Define iA32 constants, to be used by ISA transition code
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//
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_DataSelector == 0x23
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_CodeSelector == 0x1b
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_FsSelector == 0x3b
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_LdtSelector == 0x4b
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//
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// Define the IA-32 registers
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//
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rEax = r8 // v0
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rEcx = r9 // t2
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rEdx = r10 // t3
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rEbx = r11 // t4
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rEsp = r12 // sp
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rEbp = r13 // teb
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rEsi = r14 // t5
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rEdi = r15 // t6
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//
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// Define iA-32 Segment Registers mapping
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//
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rDSESFSGS = r16 // ES selector register (t7)
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rCSSSLDTTSS = r17 // CS selector register (t8)
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rEFLAG = ar24 // Eflag register
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rESD = r24 // ES Descriptor register (t15)
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rCSD = ar25 // CS Descriptor register
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rSSD = ar26 // SS Descriptor register
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rDSD = r27 // DS Descriptor register (t18)
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rFSD = r28 // FS Descriptor register (t19)
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rGSD = r29 // GS Descriptor register (t20)
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rLDTD = r30 // LDT Descriptor register (t21)
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rGDTD = r31 // GDT Descriptor register (t22)
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//
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// pointer to thread environment block
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//
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teb = r13 // per s/w convention
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kteb = ar.k3 // known "true" value (changed only by kernel)
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//
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// kernel bank shadow (hidden) registers
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//
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h16 = r16
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h17 = r17
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h18 = r18
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h19 = r19
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h20 = r20
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h21 = r21
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h22 = r22
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h23 = r23
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h24 = r24
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h25 = r25
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h26 = r26
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h27 = r27
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h28 = r28
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h29 = r29
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h30 = r30
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h31 = r31
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// Standard register aliases for procedure entry/exit
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// Should be:
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// savedpfs = loc0
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// savedbrp = loc1
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#define savedpfs loc0
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#define savedbrp loc1
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#endif
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