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761 lines
26 KiB
761 lines
26 KiB
/*++
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Copyright (c) 1992 Microsoft Corporation
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Module Name:
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et4000.h
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Abstract:
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This module contains the definitions for the code that implements the
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tseng et4000 device driver.
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Environment:
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Kernel mode
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Revision History:
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--*/
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#ifndef NO_INT10_MODE_SET
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#define INT10_MODE_SET 1
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#endif
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//////////////////////////////////////////////////////////////////////////////
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// private IOCTL info - if you touch this, do the same to the display drivers
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//
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#define IOCTL_VIDEO_GET_VIDEO_CARD_INFO \
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CTL_CODE (FILE_DEVICE_VIDEO, 2048, METHOD_BUFFERED, FILE_ANY_ACCESS)
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typedef struct _VIDEO_COPROCESSOR_INFORMATION {
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ULONG ulChipID; // ET3000, ET4000, W32, W32I, W32P, or ET6000
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ULONG ulRevLevel; // REV_A, REV_B, REV_C, REV_D, REV_UNDEF
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ULONG ulVideoMemory; // in bytes
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} VIDEO_COPROCESSOR_INFORMATION, *PVIDEO_COPROCESSOR_INFORMATION;
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typedef enum _CHIP_TYPE {
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ET3000 = 1,
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ET4000,
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W32,
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W32I,
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W32P,
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ET6000
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} CHIP_TYPE;
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typedef enum _REV_TYPE {
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REV_UNDEF = 1,
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REV_A,
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REV_B,
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REV_C,
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REV_D,
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} REV_TYPE;
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//
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// ET6000 PCI defines
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//
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#define ET6000_VENDOR_ID 0x100C
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#define ET6000_DEVICE_ID 0x3208
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//////////////////////////////////////////////////////////////////////////////
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//
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// Do full save and restore.
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//
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#define EXTENDED_REGISTER_SAVE_RESTORE 1
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//
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// BIOS Variables
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//
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#define BIOS_INFO_1 0x488
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#define PRODESIGNER_BIOS_INFO 0x4E8
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//
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// Define type of ET4000 boards
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//
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typedef enum _BOARD_TYPE {
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SPEEDSTARPLUS = 1,
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SPEEDSTAR24,
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SPEEDSTAR,
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PRODESIGNERIISEISA,
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PRODESIGNERIIS,
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PRODESIGNER2,
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TSENG3000,
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TSENG4000,
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TSENG4000W32,
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STEALTH32,
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TSENG6000,
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OTHER
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} BOARD_TYPE;
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//
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// Base address of VGA memory range. Also used as base address of VGA
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// memory when loading a font, which is done with the VGA mapped at A0000.
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//
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#define MEM_VGA 0xA0000
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#define MEM_VGA_SIZE 0x20000
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#define BANKED_FRAME_BUFFER 3
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#define LINEAR_FRAME_BUFFER 4
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//
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// W32 MMU stuff
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//
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#define PORT_IO_ADDR 0
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#define PORT_IO_LEN 0x10000
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// When we are banked
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#define BANKED_MMU_BUFFER_MEMORY_ADDR 0xB8000
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#define BANKED_MMU_BUFFER_MEMORY_LEN (0xBE000 - 0xB8000)
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#define BANKED_MMU_MEMORY_MAPPED_REGS_ADDR 0xBFF00
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#define BANKED_MMU_MEMORY_MAPPED_REGS_LEN (0xC0000 - 0xBFF00)
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#define BANKED_MMU_EXTERNAL_MAPPED_REGS_ADDR 0xBE000
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#define BANKED_MMU_EXTERNAL_MAPPED_REGS_LEN (0xBF000 - 0xBE000)
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#define BANKED_APERTURE_0_OFFSET 0x0000
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#define BANKED_APERTURE_1_OFFSET 0x2000
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#define BANKED_APERTURE_2_OFFSET 0x4000
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// When we are linear
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#define MMU_BUFFER_MEMORY_ADDR 0x200000
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#define MMU_BUFFER_MEMORY_LEN 0x180000
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#define MMU_MEMORY_MAPPED_REGS_ADDR 0x3FFF00
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#define MMU_MEMORY_MAPPED_REGS_LEN 0x000100
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#define MMU_EXTERNAL_MAPPED_REGS_ADDR 0x3FE000
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#define MMU_EXTERNAL_MAPPED_REGS_LEN 0x001000
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typedef struct {
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ULONG ulOffset;
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ULONG ulLength;
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} RANGE_OFFSETS;
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#define APERTURE_0_OFFSET 0x000000
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#define APERTURE_1_OFFSET 0x080000
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#define APERTURE_2_OFFSET 0x100000
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#define MMU_APERTURE_2_ACL_BIT 0x04
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typedef struct {
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ULONG ulPhysicalAddress;
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ULONG ulLength;
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ULONG ulInIoSpace;
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PVOID pvVirtualAddress;
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} W32_ADDRESS_MAPPING_INFORMATION, *PW32_ADDRESS_MAPPING_INFORMATION;
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//
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// Port definitions for filling the ACCESS_RANGES structure in the miniport
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// information, defines the range of I/O ports the VGA spans.
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// There is a break in the IO ports - a few ports are used for the parallel
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// port. Those cannot be defined in the ACCESS_RANGE, but are still mapped
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// so all VGA ports are in one address range.
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//
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#define VGA_BASE_IO_PORT 0x000003B0
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#define VGA_START_BREAK_PORT 0x000003BB
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#define VGA_END_BREAK_PORT 0x000003C0
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#define VGA_MAX_IO_PORT 0x000003DF
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//
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// W32 CRTCB port addresses (used for ID)
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//
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#define CRTCB_IO_PORT_BASE 0x0000217A
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#define CRTCB_IO_PORT_LEN 0x00000002
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#define CRTCB_IO_PORT_INDEX CRTCB_IO_PORT_BASE
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#define CRTCB_IO_PORT_DATA (CRTCB_IO_PORT_INDEX+1)
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#define IND_CRTCB_CHIP_ID 0xEC
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//
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// VGA register definitions
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//
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// ports in monochrome mode
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#define CRTC_ADDRESS_PORT_MONO 0x03B4 // CRT Controller Address and
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#define CRTC_DATA_PORT_MONO 0x03B5 // Data registers in mono mode
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#define MODE_CONTROL_PORT_MONO 0x03B8 // Tseng Mode Control port, used
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// here only for unlocking the
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// key so we can get at extended
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// registers
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#define FEAT_CTRL_WRITE_PORT_MONO 0x03BA // Feature Control write port
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// in mono mode
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#define INPUT_STATUS_1_MONO 0x03BA // Input Status 1 register read
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// port in mono mode
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#define ATT_INITIALIZE_PORT_MONO INPUT_STATUS_1_MONO
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// Register to read to reset
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// Attribute Controller index/data
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// toggle in mono mode
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#define HERCULES_COMPATIBILITY_PORT 0x03BF // used to unlock Tseng key to
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// get at extended ports
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#define ATT_ADDRESS_PORT 0x03C0 // Attribute Controller Address and
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#define ATT_DATA_WRITE_PORT 0x03C0 // Data registers share one port
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// for writes, but only Address is
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// readable at 0x010
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#define ATT_DATA_READ_PORT 0x03C1 // Attribute Controller Data reg is
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// readable here
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#define MISC_OUTPUT_REG_WRITE_PORT 0x03C2 // Miscellaneous Output reg write
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// port
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#define INPUT_STATUS_0_PORT 0x03C2 // Input Status 0 register read
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// port
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#define VIDEO_SUBSYSTEM_ENABLE_PORT 0x03C3 // Bit 0 enables/disables the
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// entire VGA subsystem
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#define SEQ_ADDRESS_PORT 0x03C4 // Sequence Controller Address and
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#define SEQ_DATA_PORT 0x03C5 // Data registers
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#define DAC_PIXEL_MASK_PORT 0x03C6 // DAC pixel mask reg
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#define DAC_ADDRESS_READ_PORT 0x03C7 // DAC register read index reg,
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// write-only
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#define DAC_STATE_PORT 0x03C7 // DAC state (read/write),
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// read-only
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#define DAC_ADDRESS_WRITE_PORT 0x03C8 // DAC register write index reg
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#define DAC_DATA_REG_PORT 0x03C9 // DAC data transfer reg
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#define FEAT_CTRL_READ_PORT 0x03CA // Feature Control read port
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#define MISC_OUTPUT_REG_READ_PORT 0x03CC // Miscellaneous Output reg read
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// port
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#define SEGMENT_SELECT_PORT 0x03CD // Tseng banking control register
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#define SEGMENT_SELECT_HIGH 0x03CB // Tseng W32 SegSel extension
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#define GRAPH_ADDRESS_PORT 0x03CE // Graphics Controller Address
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#define GRAPH_DATA_PORT 0x03CF // and Data registers
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// ports in color mode
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#define CRTC_ADDRESS_PORT_COLOR 0x03D4 // CRT Controller Address and
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#define CRTC_DATA_PORT_COLOR 0x03D5 // Data registers in color mode
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#define MODE_CONTROL_PORT_COLOR 0x03D8 // Tseng Mode Control port, used
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// here only for unlocking the
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// key so we can get at extended
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// registers
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#define FEAT_CTRL_WRITE_PORT_COLOR 0x03DA // Feature Control write port
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#define INPUT_STATUS_1_COLOR 0x03DA // Input Status 1 register read
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// port in color mode
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#define ATT_INITIALIZE_PORT_COLOR INPUT_STATUS_1_COLOR
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// Register to read to reset
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// Attribute Controller index/data
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// toggle in color mode
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//
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// Offsets in HardwareStateHeader->PortValue[] of save areas for non-indexed
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// VGA registers.
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//
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#define CRTC_ADDRESS_MONO_OFFSET 0x04
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#define FEAT_CTRL_WRITE_MONO_OFFSET 0x0A
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#define ATT_ADDRESS_OFFSET 0x10
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#define MISC_OUTPUT_REG_WRITE_OFFSET 0x12
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#define VIDEO_SUBSYSTEM_ENABLE_OFFSET 0x13
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#define SEQ_ADDRESS_OFFSET 0x14
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#define DAC_PIXEL_MASK_OFFSET 0x16
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#define DAC_STATE_OFFSET 0x17
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#define DAC_ADDRESS_WRITE_OFFSET 0x18
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#define GRAPH_ADDRESS_OFFSET 0x1E
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#define CRTC_ADDRESS_COLOR_OFFSET 0x24
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#define FEAT_CTRL_WRITE_COLOR_OFFSET 0x2A
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//
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// VGA indexed register indexes.
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//
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#define IND_CURSOR_START 0x0A // index in CRTC of the Cursor Start
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#define IND_CURSOR_END 0x0B // and End registers
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#define IND_CURSOR_HIGH_LOC 0x0E // index in CRTC of the Cursor Location
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#define IND_CURSOR_LOW_LOC 0x0F // High and Low Registers
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#define IND_VSYNC_END 0x11 // index in CRTC of the Vertical Sync
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// End register, which has the bit
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// that protects/unprotects CRTC
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// index registers 0-7
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#define IND_SET_RESET_ENABLE 0x01 // index of Set/Reset Enable reg in GC
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#define IND_DATA_ROTATE 0x03 // index of Data Rotate reg in GC
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#define IND_READ_MAP 0x04 // index of Read Map reg in Graph Ctlr
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#define IND_GRAPH_MODE 0x05 // index of Mode reg in Graph Ctlr
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#define IND_GRAPH_MISC 0x06 // index of Misc reg in Graph Ctlr
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#define IND_BIT_MASK 0x08 // index of Bit Mask reg in Graph Ctlr
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#define IND_SYNC_RESET 0x00 // index of Sync Reset reg in Seq
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#define IND_MAP_MASK 0x02 // index of Map Mask in Sequencer
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#define IND_MEMORY_MODE 0x04 // index of Memory Mode reg in Seq
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#define IND_STATE_CONTROL 0x06 // index of TS State Control reg in Seq
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#define IND_TS_AUX_MODE 0x07 // index of TS Aux Mode reg in Seq
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#define IND_CRTC_PROTECT 0x11 // index of reg containing regs 0-7 in
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// CRTC
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#define IND_RAS_CAS_CONFIG 0x32 // index of RAS/CAS Config reg in CRTC
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#define IND_EXT_START_ADDR 0x33 // index of Extended Start Address reg
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// in CRTC
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#define IND_CRTC_COMPAT 0x34 // index of CRTC Compatibility reg
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// in CRTC
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#define IND_OFLOW_HIGH 0x35 // index of Overflow High reg in CRTC
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#define IND_VID_SYS_CONFIG_1 0x36 // index of Video System Configuration
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#define IND_VID_SYS_CONFIG_2 0x37 // 1 & 2 registers in CRTC
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#define IND_ATC_MISC 0x16 // index of Miscellaneous reg in ATC
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#define START_SYNC_RESET_VALUE 0x01 // value for Sync Reset reg to start
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// synchronous reset
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#define END_SYNC_RESET_VALUE 0x03 // value for Sync Reset reg to end
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// synchronous reset
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#define UNLOCK_KEY_1 0x03 // value to output to Herc Compat
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// register as first step in unlocking
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// key so Tseng registers can be set
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#define UNLOCK_KEY_2 0xA0 // value to output to Mode Control Port
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// register as 2nd step in unlocking
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// key so Tseng registers can be set
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#define LOCK_KEY_1 0x00 // value to output to Herc Compat
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// register as first step in locking
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// key so Tseng registers can't be set
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#define LOCK_KEY_2 0x00 // value to output to Mode Control Port
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// register as 2nd step in locking
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// key so Tseng registers can't be set
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#define HERCULES_COMPATIBILITY_DEFAULT 0x00
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// value to output to Herc Compat
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// register to put back to MDA
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// compatibility
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#define MODE_CONTROL_PORT_COLOR_DEFAULT 0x00
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#define MODE_CONTROL_PORT_MONO_DEFAULT 0x00
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// values to output to CGA and MDA mode
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// registers to put to default state
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// (video disabled).
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//
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// Values for Attribute Controller Index register to turn video off
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// and on, by setting bit 5 to 0 (off) or 1 (on).
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//
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#define VIDEO_DISABLE 0
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#define VIDEO_ENABLE 0x20
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// Masks to keep only the significant bits of the Graphics Controller and
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// Sequencer Address registers. Masking is necessary because some VGAs, such
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// as S3-based ones, don't return unused bits set to 0, and some SVGAs use
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// these bits if extensions are enabled.
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//
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#define GRAPH_ADDR_MASK 0x0F
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#define SEQ_ADDR_MASK 0x07
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//
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// Mask used to toggle Chain4 bit in the Sequencer's Memory Mode register.
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//
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#define CHAIN4_MASK 0x08
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//
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// Value written to the Read Map register when identifying the existence of
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// a VGA in VgaInitialize. This value must be different from the final test
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// value written to the Bit Mask in that routine.
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//
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#define READ_MAP_TEST_SETTING 0x03
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//
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// Default text mode setting for various registers, used to restore their
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// states if VGA detection fails after they've been modified.
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//
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#define MEMORY_MODE_TEXT_DEFAULT 0x02
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#define BIT_MASK_DEFAULT 0xFF
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#define READ_MAP_DEFAULT 0x00
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//
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// Palette-related info.
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//
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//
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// Highest valid DAC color register index.
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//
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#define VIDEO_MAX_COLOR_REGISTER 0xFF
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//
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// Highest valid palette register index
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//
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#define VIDEO_MAX_PALETTE_REGISTER 0x0F
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//
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// Indices for type of memory mapping; used in ModesVGA[], must match
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// MemoryMap[].
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//
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typedef enum _VIDEO_MEMORY_MAP {
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MemMap_Mono,
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MemMap_CGA,
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MemMap_VGA
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} VIDEO_MEMORY_MAP, *PVIDEO_MEMORY_MAP;
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//
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// Memory map table definition
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//
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typedef struct {
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ULONG MaxSize; // Maximum addressable size of memory
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ULONG Start; // Start address of display memory
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} MEMORYMAPS;
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//
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// For a mode, the type of banking supported. Controls the information
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// returned in VIDEO_BANK_SELECT. PlanarHCBanking includes NormalBanking.
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//
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typedef enum _BANK_TYPE {
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NoBanking = 0,
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MemMgrBanking,
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NormalBanking,
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PlanarHCBanking
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} BANK_TYPE, *PBANK_TYPE;
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//
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// Structure used to describe each video mode in ModesVGA[].
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//
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typedef struct {
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USHORT fbType; // color or monochrome, text or graphics, via
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// VIDEO_MODE_COLOR and VIDEO_MODE_GRAPHICS
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USHORT numPlanes; // # of video memory planes
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USHORT bitsPerPlane; // # of bits of color in each plane
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SHORT col; // # of text columns across screen with default font
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SHORT row; // # of text rows down screen with default font
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USHORT hres; // # of pixels across screen
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USHORT vres; // # of scan lines down screen
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USHORT wbytes; // # of bytes from start of one scan line to start of next
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ULONG sbytes; // total size of addressable display memory in bytes
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ULONG Frequency; // Vertical Frequency
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ULONG Interlaced; // Determines if the mode is interlaced or not
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BANK_TYPE banktype; // NoBanking, NormalBanking, PlanarHCBanking
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VIDEO_MEMORY_MAP MemMap; // index from VIDEO_MEMORY_MAP of memory
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// mapping used by this mode
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BOOLEAN ValidMode; // Determines which modes are valid.
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ULONG Int10ModeNumber; // Mode number via Int 10
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PUSHORT CmdStrings; // pointer to array of register-setting commands
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} VIDEOMODE, *PVIDEOMODE;
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//
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// Mode into which to put the VGA before starting a VDM, so it's a plain
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// vanilla VGA. (This is the mode's index in ModesVGA[], currently standard
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// 80x25 text mode.)
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//
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#define DEFAULT_MODE 0
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//
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// Info used by the Validator functions and save/restore code.
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// Structure used to trap register accesses that must be done atomically.
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//
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//
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// Number of each type of indexed register in a standard VGA, used by
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// validator and state save/restore functions.
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//
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// Note: VDMs currently only support basic VGAs only.
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//
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#define VGA_NUM_SEQUENCER_PORTS 5
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#define VGA_NUM_CRTC_PORTS 25
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#define VGA_NUM_GRAPH_CONT_PORTS 9
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#define VGA_NUM_ATTRIB_CONT_PORTS 21
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#define VGA_NUM_DAC_ENTRIES 256
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#ifdef EXTENDED_REGISTER_SAVE_RESTORE
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//
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// Indices to start save/restore in extension registers:
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// For both chip types
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#define ET4000_SEQUENCER_EXT_START 0x06
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#define ET4000_SEQUENCER_EXT_END 0x07
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#define ET4000_CRTC_EXT_START 0x31
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#define ET4000_CRTC_EXT_END 0x37
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#define ET4000_CRTC_1_EXT_START 0x3F
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#define ET4000_CRTC_1_EXT_END 0x3F
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#define ET4000_ATTRIB_EXT_START 0x16
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#define ET4000_ATTRIB_EXT_END 0x16
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//
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// Number of extended regs for both chip types.
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//
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#define ET4000_NUM_SEQUENCER_EXT_PORTS (ET4000_SEQUENCER_EXT_END - ET4000_SEQUENCER_EXT_START + 1)
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#define ET4000_NUM_CRTC_EXT_PORTS (ET4000_CRTC_EXT_END - ET4000_CRTC_EXT_START + 1) + \
|
|
(ET4000_CRTC_1_EXT_END - ET4000_CRTC_1_EXT_START + 1)
|
|
#define ET4000_NUM_ATTRIB_EXT_PORTS (ET4000_ATTRIB_EXT_END - ET4000_ATTRIB_EXT_START + 1)
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|
|
|
//
|
|
// set values for save/restore area based on largest value for a chipset.
|
|
//
|
|
|
|
#define EXT_NUM_GRAPH_CONT_PORTS 0
|
|
#define EXT_NUM_SEQUENCER_PORTS ET4000_NUM_SEQUENCER_EXT_PORTS
|
|
#define EXT_NUM_CRTC_PORTS ET4000_NUM_CRTC_EXT_PORTS
|
|
#define EXT_NUM_ATTRIB_CONT_PORTS ET4000_NUM_ATTRIB_EXT_PORTS
|
|
#define EXT_NUM_DAC_ENTRIES 0
|
|
|
|
#else
|
|
|
|
#define EXT_NUM_GRAPH_CONT_PORTS 0
|
|
#define EXT_NUM_SEQUENCER_PORTS 0
|
|
#define EXT_NUM_CRTC_PORTS 0
|
|
#define EXT_NUM_ATTRIB_CONT_PORTS 0
|
|
#define EXT_NUM_DAC_ENTRIES 0
|
|
|
|
#endif
|
|
|
|
|
|
#define VGA_MAX_VALIDATOR_DATA 100
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|
|
|
#define VGA_VALIDATOR_UCHAR_ACCESS 1
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|
#define VGA_VALIDATOR_USHORT_ACCESS 2
|
|
#define VGA_VALIDATOR_ULONG_ACCESS 3
|
|
|
|
typedef struct _VGA_VALIDATOR_DATA {
|
|
ULONG Port;
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|
UCHAR AccessType;
|
|
ULONG Data;
|
|
} VGA_VALIDATOR_DATA, *PVGA_VALIDATOR_DATA;
|
|
|
|
//
|
|
// Number of bytes to save in each plane.
|
|
//
|
|
|
|
#define VGA_PLANE_SIZE 0x10000
|
|
|
|
//
|
|
// These constants determine the offsets within the
|
|
// VIDEO_HARDWARE_STATE_HEADER structure that are used to save and
|
|
// restore the VGA's state.
|
|
//
|
|
|
|
#define VGA_HARDWARE_STATE_SIZE sizeof(VIDEO_HARDWARE_STATE_HEADER)
|
|
|
|
#define VGA_BASIC_SEQUENCER_OFFSET (VGA_HARDWARE_STATE_SIZE + 0)
|
|
#define VGA_BASIC_CRTC_OFFSET (VGA_BASIC_SEQUENCER_OFFSET + \
|
|
VGA_NUM_SEQUENCER_PORTS)
|
|
#define VGA_BASIC_GRAPH_CONT_OFFSET (VGA_BASIC_CRTC_OFFSET + \
|
|
VGA_NUM_CRTC_PORTS)
|
|
#define VGA_BASIC_ATTRIB_CONT_OFFSET (VGA_BASIC_GRAPH_CONT_OFFSET + \
|
|
VGA_NUM_GRAPH_CONT_PORTS)
|
|
#define VGA_BASIC_DAC_OFFSET (VGA_BASIC_ATTRIB_CONT_OFFSET + \
|
|
VGA_NUM_ATTRIB_CONT_PORTS)
|
|
#define VGA_BASIC_LATCHES_OFFSET (VGA_BASIC_DAC_OFFSET + \
|
|
(3 * VGA_NUM_DAC_ENTRIES))
|
|
|
|
#define VGA_EXT_SEQUENCER_OFFSET (VGA_BASIC_LATCHES_OFFSET + 4)
|
|
#define VGA_EXT_CRTC_OFFSET (VGA_EXT_SEQUENCER_OFFSET + \
|
|
EXT_NUM_SEQUENCER_PORTS)
|
|
#define VGA_EXT_GRAPH_CONT_OFFSET (VGA_EXT_CRTC_OFFSET + \
|
|
EXT_NUM_CRTC_PORTS)
|
|
#define VGA_EXT_ATTRIB_CONT_OFFSET (VGA_EXT_GRAPH_CONT_OFFSET +\
|
|
EXT_NUM_GRAPH_CONT_PORTS)
|
|
#define VGA_EXT_DAC_OFFSET (VGA_EXT_ATTRIB_CONT_OFFSET + \
|
|
EXT_NUM_ATTRIB_CONT_PORTS)
|
|
|
|
#define VGA_VALIDATOR_OFFSET (VGA_EXT_DAC_OFFSET + 4 * EXT_NUM_DAC_ENTRIES)
|
|
|
|
#define VGA_VALIDATOR_AREA_SIZE sizeof (ULONG) + (VGA_MAX_VALIDATOR_DATA * \
|
|
sizeof (VGA_VALIDATOR_DATA)) + \
|
|
sizeof (ULONG) + \
|
|
sizeof (ULONG) + \
|
|
sizeof (PVIDEO_ACCESS_RANGE)
|
|
|
|
#define VGA_MISC_DATA_AREA_OFFSET VGA_VALIDATOR_OFFSET + VGA_VALIDATOR_AREA_SIZE
|
|
|
|
#define VGA_MISC_DATA_AREA_SIZE 0
|
|
|
|
#define VGA_PLANE_0_OFFSET VGA_MISC_DATA_AREA_OFFSET + VGA_MISC_DATA_AREA_SIZE
|
|
|
|
#define VGA_PLANE_1_OFFSET VGA_PLANE_0_OFFSET + VGA_PLANE_SIZE
|
|
#define VGA_PLANE_2_OFFSET VGA_PLANE_1_OFFSET + VGA_PLANE_SIZE
|
|
#define VGA_PLANE_3_OFFSET VGA_PLANE_2_OFFSET + VGA_PLANE_SIZE
|
|
|
|
//
|
|
// Space needed to store all state data.
|
|
//
|
|
|
|
#define VGA_TOTAL_STATE_SIZE VGA_PLANE_3_OFFSET + VGA_PLANE_SIZE
|
|
|
|
|
|
//
|
|
// Device extension for the driver object. This data is only used
|
|
// locally, so this structure can be added to as needed.
|
|
//
|
|
|
|
typedef struct _HW_DEVICE_EXTENSION {
|
|
|
|
PUCHAR IOAddress; // base I/O address of VGA ports
|
|
PVOID VideoMemoryAddress; // base virtual memory address of VGA memory
|
|
ULONG AdapterMemorySize; // size, in bytes, of the memory on the
|
|
// board.
|
|
ULONG ModeIndex; // index of current mode in ModesVGA[]
|
|
ULONG NumAvailableModes; // number of valid modes on this device
|
|
PVIDEOMODE CurrentMode; // pointer to VIDEOMODE structure for
|
|
// current mode.
|
|
|
|
CHIP_TYPE ulChipID;
|
|
REV_TYPE ulRevLevel;
|
|
|
|
USHORT FontPelColumns; // Width of the font in pels
|
|
USHORT FontPelRows; // height of the font in pels
|
|
|
|
VIDEO_CURSOR_POSITION CursorPosition; // current cursor position
|
|
|
|
|
|
UCHAR CursorEnable; // whether cursor is enabled or not
|
|
UCHAR CursorTopScanLine; // Cursor Start register setting (top scan)
|
|
UCHAR CursorBottomScanLine; // Cursor End register setting (bottom scan)
|
|
|
|
UCHAR BoardID; // Used to Identify Diamond boards
|
|
|
|
PHYSICAL_ADDRESS PhysicalVideoMemoryBase; // physical memory address and
|
|
ULONG PhysicalVideoMemoryLength; // length of display memory
|
|
PHYSICAL_ADDRESS PhysicalFrameBase; // physical memory address and
|
|
ULONG PhysicalFrameLength; // length of display memory for the
|
|
// current mode.
|
|
|
|
PUSHORT BiosArea; // address of the BIOS area
|
|
USHORT OriginalBiosData; // Orignal value in the Bios data area.
|
|
|
|
BOOLEAN bLinearModeSupported; // Do we support linear modes?
|
|
BOOLEAN bInLinearMode; // Are we currently in a linear mode?
|
|
ULONG ulSlot; // the slot that the card is in
|
|
|
|
//
|
|
// These 4 fields must be at the end of the device extension and must be
|
|
// kept in this order since this data will be copied to and from the save
|
|
// state buffer that is passed to and from the VDM.
|
|
//
|
|
|
|
ULONG TrappedValidatorCount; // number of entries in the Trapped
|
|
// validator data Array.
|
|
VGA_VALIDATOR_DATA TrappedValidatorData[VGA_MAX_VALIDATOR_DATA];
|
|
// Data trapped by the validator routines
|
|
// but not yet played back into the VGA
|
|
// register.
|
|
|
|
ULONG SequencerAddressValue; // Determines if the Sequencer Address Port
|
|
// is currently selecting the SyncReset data
|
|
// register.
|
|
|
|
ULONG CurrentNumVdmAccessRanges; // Number of access ranges in
|
|
// the access range array pointed
|
|
// to by the next field
|
|
PVIDEO_ACCESS_RANGE CurrentVdmAccessRange; // Access range currently
|
|
// associated to the VDM
|
|
|
|
} HW_DEVICE_EXTENSION, *PHW_DEVICE_EXTENSION;
|
|
|
|
|
|
//
|
|
// Function prototypes.
|
|
//
|
|
|
|
//
|
|
// Entry points for the VGA validator. Used in VgaEmulatorAccessEntries[].
|
|
//
|
|
|
|
VP_STATUS
|
|
VgaValidatorUcharEntry (
|
|
ULONG Context,
|
|
ULONG Port,
|
|
UCHAR AccessMode,
|
|
PUCHAR Data
|
|
);
|
|
|
|
VP_STATUS
|
|
VgaValidatorUshortEntry (
|
|
ULONG Context,
|
|
ULONG Port,
|
|
UCHAR AccessMode,
|
|
PUSHORT Data
|
|
);
|
|
|
|
VP_STATUS
|
|
VgaValidatorUlongEntry (
|
|
ULONG Context,
|
|
ULONG Port,
|
|
UCHAR AccessMode,
|
|
PULONG Data
|
|
);
|
|
|
|
BOOLEAN
|
|
VgaPlaybackValidatorData (
|
|
PVOID Context
|
|
);
|
|
|
|
//
|
|
// Bank switch code start and end labels, define in HARDWARE.ASM
|
|
//
|
|
|
|
extern UCHAR BankSwitchStart;
|
|
extern UCHAR PlanarHCBankSwitchStart;
|
|
extern UCHAR EnablePlanarHCStart;
|
|
extern UCHAR DisablePlanarHCStart;
|
|
extern UCHAR BankSwitchEnd;
|
|
|
|
//
|
|
// Vga init scripts for font loading
|
|
//
|
|
|
|
extern USHORT EnableA000Data[];
|
|
extern USHORT DisableA000Color[];
|
|
|
|
extern MEMORYMAPS MemoryMaps[];
|
|
|
|
extern VIDEOMODE ModesVGA[];
|
|
extern ULONG NumVideoModes;
|
|
|
|
extern RANGE_OFFSETS RangeOffsets[2][2];
|
|
|
|
#define NUM_VGA_ACCESS_RANGES 3
|
|
extern VIDEO_ACCESS_RANGE VgaAccessRange[];
|
|
|
|
#define VGA_NUM_EMULATOR_ACCESS_ENTRIES 6
|
|
extern EMULATOR_ACCESS_ENTRY VgaEmulatorAccessEntries[];
|
|
|
|
#define NUM_MINIMAL_VGA_VALIDATOR_ACCESS_RANGE 4
|
|
extern VIDEO_ACCESS_RANGE MinimalVgaValidatorAccessRange[];
|
|
|
|
#define NUM_FULL_VGA_VALIDATOR_ACCESS_RANGE 2
|
|
extern VIDEO_ACCESS_RANGE FullVgaValidatorAccessRange[];
|
|
|
|
|
|
//
|
|
// functions used in both modules.
|
|
//
|
|
|
|
VOID
|
|
UnlockET4000ExtendedRegs(
|
|
PHW_DEVICE_EXTENSION HwDeviceExtension
|
|
);
|
|
|
|
VOID
|
|
LockET4000ExtendedRegs(
|
|
PHW_DEVICE_EXTENSION HwDeviceExtension
|
|
);
|
|
|
|
#define VESA_POWER_FUNCTION 0x4f10
|
|
#define VESA_POWER_ON 0x0000
|
|
#define VESA_POWER_STANDBY 0x0100
|
|
#define VESA_POWER_SUSPEND 0x0200
|
|
#define VESA_POWER_OFF 0x0400
|
|
#define VESA_GET_POWER_FUNC 0x0000
|
|
#define VESA_SET_POWER_FUNC 0x0001
|
|
#define VESA_STATUS_SUCCESS 0x004f
|
|
|
|
#define QUERY_MONITOR_ID 0x22446688
|
|
#define QUERY_NONDDC_MONITOR_ID 0x11223344
|