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894 lines
22 KiB
894 lines
22 KiB
/*++
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Copyright (c) 1989 Microsoft Corporation
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Module Name:
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pccardc.c
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Abstract:
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This module contains the C code to set up PcCard (pcmcia, cardbus)
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configuration data.
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Author:
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Neil Sandlin (neilsa) 16-Dec-1998
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(DetectIRQMap, ToggleIRQLine were copied from win9x)
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Revision History:
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--*/
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#include "hwdetect.h"
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#include "pccard.h"
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#include <string.h>
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extern UCHAR DisablePccardIrqScan;
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extern BOOLEAN SystemHas8259;
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extern BOOLEAN SystemHas8253;
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CARDBUS_BRIDGE_DEVTYPE CBTable[] = {
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{0x11101013, DEVTYPE_CL_PD6832},
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{0x11121013, DEVTYPE_CL_PD6834},
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{0x11111013, DEVTYPE_CL_PD6833},
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{0xAC12104C, DEVTYPE_TI_PCI1130},
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{0xAC15104C, DEVTYPE_TI_PCI1131},
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{0xAC13104C, DEVTYPE_TI_PCI1031},
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{0,0}};
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FPFWCONFIGURATION_COMPONENT_DATA ControllerList = NULL;
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#define LEGACY_BASE_LIST_SIZE 10
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USHORT LegacyBaseList[LEGACY_BASE_LIST_SIZE] = {0};
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USHORT LegacyBaseListCount = 0;
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VOID
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SetPcCardConfigurationData(
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PPCCARD_INFORMATION PcCardInfo
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)
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/*++
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Routine Description:
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This routine creates a structure containing the result of the
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irq detection, and links it onto our running list. This list
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eventually will show up in the registry under hardware
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descriptions.
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Arguments:
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PcCardInfo - Structure containing the results of detection
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Returns:
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None.
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--*/
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{
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FPFWCONFIGURATION_COMPONENT_DATA CurrentEntry;
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static FPFWCONFIGURATION_COMPONENT_DATA PreviousEntry = NULL;
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FPFWCONFIGURATION_COMPONENT Component;
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FPHWRESOURCE_DESCRIPTOR_LIST DescriptorList;
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CHAR Identifier[32];
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FPCHAR IdentifierString;
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USHORT Length;
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CM_PCCARD_DEVICE_DATA far *PcCardData;
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CurrentEntry = (FPFWCONFIGURATION_COMPONENT_DATA)HwAllocateHeap (
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sizeof(FWCONFIGURATION_COMPONENT_DATA), TRUE);
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if (!ControllerList) {
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ControllerList = CurrentEntry;
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}
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Component = &CurrentEntry->ComponentEntry;
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Component->Class = ControllerClass;
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Component->Type = OtherController;
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strcpy (Identifier, "PcCardController");
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Length = strlen(Identifier) + 1;
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IdentifierString = (FPCHAR)HwAllocateHeap(Length, FALSE);
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_fstrcpy(IdentifierString, Identifier);
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Component->IdentifierLength = Length;
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Component->Identifier = IdentifierString;
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Length = sizeof(HWRESOURCE_DESCRIPTOR_LIST) + sizeof(CM_PCCARD_DEVICE_DATA);
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DescriptorList = (FPHWRESOURCE_DESCRIPTOR_LIST)HwAllocateHeap(
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Length,
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TRUE);
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CurrentEntry->ConfigurationData = DescriptorList;
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Component->ConfigurationDataLength = Length;
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DescriptorList->Count = 1;
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DescriptorList->PartialDescriptors[0].Type = RESOURCE_DEVICE_DATA;
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DescriptorList->PartialDescriptors[0].u.DeviceSpecificData.DataSize =
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sizeof(CM_PCCARD_DEVICE_DATA);
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PcCardData = (CM_PCCARD_DEVICE_DATA far *)(DescriptorList + 1);
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PcCardData->Flags = PcCardInfo->Flags;
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PcCardData->ErrorCode = PcCardInfo->ErrorCode;
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PcCardData->DeviceId = PcCardInfo->DeviceId;
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PcCardData->LegacyBaseAddress = (ULONG) PcCardInfo->IoBase;
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if (PcCardInfo->Flags & PCCARD_DEVICE_PCI) {
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PcCardData->BusData = PcCardInfo->PciCfg1.u.bits.BusNumber |
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PcCardInfo->PciCfg1.u.bits.DeviceNumber << 8 |
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PcCardInfo->PciCfg1.u.bits.FunctionNumber << 16;
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}
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_fmemcpy(PcCardData->IRQMap, PcCardInfo->abIRQMap, 16);
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if (PreviousEntry) {
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PreviousEntry->Sibling = CurrentEntry;
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}
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PreviousEntry = CurrentEntry;
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}
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BOOLEAN
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IsOnLegacyBaseList(
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USHORT IoBase
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)
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/*++
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Routine Description:
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This routine runs our list of legacy base addresses to see if we
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have looked at the address before.
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Arguments:
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IoBase = base address to map
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Returns:
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TRUE if the base address is already on the list
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--*/
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{
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USHORT i;
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for (i = 0; i<LegacyBaseListCount; i++) {
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if (IoBase == LegacyBaseList[i]) {
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return TRUE;
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}
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}
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return FALSE;
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}
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BOOLEAN
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SetLegacyBaseList(
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USHORT IoBase
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)
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/*++
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Routine Description:
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This routine remembers the legacy base addresses that we have looked
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at so far so we don't keep mapping the same address.
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NOTE: We are using a DUMB mechanism that only builds the list in a
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fixed array. We could write some generic code which creates
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a linked list, but since the heap routines in ntdetect are also
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dumb, it makes it not possible to free the list. It's just not worth
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it.
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Arguments:
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IoBase = base address to map
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Returns:
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TRUE if the base address is unique to this point
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FALSE if the base address already exists on the list
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--*/
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{
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if (IsOnLegacyBaseList(IoBase)) {
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return FALSE;
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}
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if (LegacyBaseListCount < LEGACY_BASE_LIST_SIZE) {
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LegacyBaseList[LegacyBaseListCount++] = IoBase;
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}
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// note, we return true even if we overflow the list
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return TRUE;
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}
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VOID
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MapPcCardController(
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PPCCARD_INFORMATION PcCardInfo
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)
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/*++
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Routine Description:
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This routine is the entry for doing ISA IRQ detection for PcCard
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controllers.
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Arguments:
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PcCardInfo - Structure defining the device to run detection on
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Returns:
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None.
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--*/
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{
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USHORT wDetected;
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USHORT i;
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PcCardInfo->ErrorCode = 0;
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for (i=0; i<16; i++) {
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PcCardInfo->abIRQMap[i]=0;
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}
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if (!PcCardInfo->IoBase) {
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PcCardInfo->Flags |= PCCARD_MAP_ERROR;
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PcCardInfo->ErrorCode = PCCARD_NO_LEGACY_BASE;
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} else if (!SetLegacyBaseList(PcCardInfo->IoBase)) {
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PcCardInfo->Flags |= PCCARD_MAP_ERROR;
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PcCardInfo->ErrorCode = PCCARD_DUP_LEGACY_BASE;
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}
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if (!(PcCardInfo->Flags & PCCARD_MAP_ERROR)) {
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PcCardInfo->wValidIRQs = PCCARD_POSSIBLE_IRQS;
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#if DBG
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BlPrint("Going to detect...\n");
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#endif
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//
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// Do the IRQ detection
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//
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wDetected = DetectIRQMap(PcCardInfo);
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#if DBG
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BlPrint("Detect IRQ Map returns %x on iobase %x\n", wDetected, PcCardInfo->IoBase);
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#endif
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if (!wDetected) {
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PcCardInfo->ErrorCode = PCCARD_MAP_ZERO;
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}
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}
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#if DBG
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if (PcCardInfo->Flags & PCCARD_MAP_ERROR) {
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BlPrint("Error mapping device, code=%x\n", PcCardInfo->ErrorCode);
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}
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#endif
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//
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// Report the results
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//
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SetPcCardConfigurationData(PcCardInfo);
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}
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VOID
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LookForPciCardBusBridges(
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USHORT BusStart,
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USHORT BusEnd,
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)
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/*++
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Routine Description:
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This routine is the entry for doing ISA IRQ detection for PCI-based
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cardbus controllers.
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Arguments:
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Bus = PCI Bus number to scan
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Returns:
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None.
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--*/
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{
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PCCARD_INFORMATION PcCardInfo = {0};
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USHORT Device, Function;
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UCHAR HeaderType;
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UCHAR SecBus, SubBus;
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USHORT VendorId;
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USHORT DeviceId;
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ULONG LegacyBaseAddress;
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USHORT i;
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USHORT Bus;
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#if DBG
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BlPrint("LookForPciCardBusBridges %x-%x\n", BusStart, BusEnd);
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#endif
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for (Bus = BusStart; Bus <= BusEnd; Bus++) {
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PcCardInfo.PciCfg1.u.AsULONG = 0;
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PcCardInfo.PciCfg1.u.bits.BusNumber = Bus;
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PcCardInfo.PciCfg1.u.bits.Enable = TRUE;
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for (Device = 0; Device < PCI_MAX_DEVICES; Device++) {
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PcCardInfo.PciCfg1.u.bits.DeviceNumber = Device;
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for (Function = 0; Function < PCI_MAX_FUNCTION; Function++) {
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PcCardInfo.PciCfg1.u.bits.FunctionNumber = Function;
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VendorId = 0xffff;
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GetPciConfigSpace(&PcCardInfo, CFGSPACE_VENDOR_ID, &VendorId, sizeof(VendorId));
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if ((VendorId == 0xffff) || (VendorId == 0)) {
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if (Function == 0) {
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break;
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} else {
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continue;
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}
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}
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GetPciConfigSpace(&PcCardInfo, CFGSPACE_DEVICE_ID, &DeviceId, sizeof(DeviceId));
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GetPciConfigSpace(&PcCardInfo, CFGSPACE_HEADER_TYPE, &HeaderType, sizeof(HeaderType));
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switch(HeaderType & 0x7f) {
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case PCI_CARDBUS_BRIDGE_TYPE:
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#if DBG
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BlPrint("%x.%x.%x : DeviceID = %lx (CardBus Bridge)\n", Bus, Device, Function, DeviceId);
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#endif
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PcCardInfo.DeviceId = (ULONG) (VendorId << 16) | DeviceId;
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PcCardInfo.Flags = PCCARD_DEVICE_PCI;
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//
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// See if this is a special cased controller
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//
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PcCardInfo.bDevType = DEVTYPE_GENERIC_CARDBUS;
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i = 0;
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while (CBTable[i].DeviceId != 0) {
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if (DeviceId == CBTable[i].DeviceId) {
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PcCardInfo.bDevType = CBTable[i].bDevType;
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break;
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}
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i++;
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}
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GetPciConfigSpace(&PcCardInfo, CFGSPACE_LEGACY_MODE_BASE_ADDR, &LegacyBaseAddress, 4);
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PcCardInfo.IoBase = (USHORT) (LegacyBaseAddress & ~1);
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MapPcCardController(&PcCardInfo);
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break;
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case PCI_BRIDGE_TYPE:
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#if DBG
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BlPrint("%x.%x.%x : DeviceID = %lx (Pci-Pci Bridge)\n", Bus, Device, Function, DeviceId);
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#endif
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GetPciConfigSpace(&PcCardInfo, CFGSPACE_SECONDARY_BUS, &SecBus, sizeof(SecBus));
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GetPciConfigSpace(&PcCardInfo, CFGSPACE_SUBORDINATE_BUS, &SubBus, sizeof(SubBus));
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if ((SecBus <= Bus) || (SubBus <= Bus) || (SubBus < SecBus)) {
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break;
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}
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//
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// Be conservative on stack space, only look one level deep
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//
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if (Bus > 0) {
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break;
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}
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LookForPciCardBusBridges(SecBus, SubBus);
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break;
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}
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}
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}
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}
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}
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VOID
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LookForPcicControllers(
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VOID
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)
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/*++
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Routine Description:
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This routine is the entry for doing ISA IRQ detection for PCIC
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controllers.
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Arguments:
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None.
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Returns:
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None.
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--*/
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{
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PCCARD_INFORMATION PcCardInfo = {0};
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USHORT IoBase;
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UCHAR id;
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for (IoBase = 0x3e0; IoBase < 0x3e6; IoBase+=2) {
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if (IsOnLegacyBaseList(IoBase)) {
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continue;
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}
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PcCardInfo.Flags = 0;
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PcCardInfo.IoBase = IoBase;
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PcCardInfo.bDevType = DEVTYPE_GENERIC_PCIC;
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id = PcicReadSocket(&PcCardInfo, EXCAREG_IDREV);
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switch (id) {
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case PCIC_REVISION:
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case PCIC_REVISION2:
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case PCIC_REVISION3:
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#if DBG
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BlPrint("Pcic Controller at base %x, rev(%x)\n", IoBase, id);
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#endif
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MapPcCardController(&PcCardInfo);
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break;
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#if DBG
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default:
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BlPrint("Not mapping base %x, return is (%x)\n", IoBase, id);
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#endif
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}
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}
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}
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FPFWCONFIGURATION_COMPONENT_DATA
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GetPcCardInformation(
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VOID
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)
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/*++
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Routine Description:
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This routine is the entry for doing ISA IRQ detection for PcCard
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controllers.
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Arguments:
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None.
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Returns:
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A pointer to a pccard component structure, if IRQ's were properly detected.
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Otherwise a NULL pointer is returned.
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--*/
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{
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PCCARD_INFORMATION PcCardInfo = {0};
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UCHAR ErrorCode = 0;
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//
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// Check for things which would prevent us from attempting
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// the irq detection
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//
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if (DisablePccardIrqScan == 1) {
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ErrorCode = PCCARD_SCAN_DISABLED;
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} else if (!SystemHas8259) {
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ErrorCode = PCCARD_NO_PIC;
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} else if (!SystemHas8253) {
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ErrorCode = PCCARD_NO_TIMER;
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}
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//
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// If things look ok so far, do the detection
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//
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if (!ErrorCode) {
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#if DBG
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BlPrint("press any key to continue...\n");
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while ( !HwGetKey() ) ; // wait until key pressed to continue
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clrscrn();
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BlPrint("Looking for PcCard Controllers...\n");
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#endif
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//
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// Look first for cardbus
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//
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LookForPciCardBusBridges(0,0);
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//
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// Now check for regular pcic devices
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//
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LookForPcicControllers();
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#if DBG
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BlPrint("press any key to continue...\n");
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while ( !HwGetKey() ) ; // wait until key pressed to continue
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#endif
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if (!ControllerList) {
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ErrorCode = PCCARD_NO_CONTROLLERS;
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}
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}
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if (ErrorCode) {
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//
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// Something when wrong, so write a single entry to
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// allow someone to see what the error was
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//
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PcCardInfo.Flags |= PCCARD_MAP_ERROR;
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PcCardInfo.ErrorCode = ErrorCode;
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SetPcCardConfigurationData(&PcCardInfo);
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}
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return ControllerList;
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}
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USHORT
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DetectIRQMap(
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PPCCARD_INFORMATION pa
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)
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/*++
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Routine Description:
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This routine detects the IRQ mapping of the specified cardbus controller.
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Note that the controller is in PCIC mode.
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Arguments:
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pa -> ADAPTER structure
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Returns:
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returns detected IRQ bit mask
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--*/
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{
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USHORT wRealIRQMask = 0;
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USHORT wData;
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UCHAR bData;
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BOOLEAN fTINMIBug = FALSE;
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UCHAR i;
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USHORT wIRQMask, wRealIRQ, w;
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if (pa->bDevType == DEVTYPE_CL_PD6832)
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{
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//enable CSC IRQ routing just for IRQ detection
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GetPciConfigSpace(pa, CFGSPACE_BRIDGE_CTRL, &wData, sizeof(wData));
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wData |= BCTRL_CL_CSCIRQROUTING_ENABLE;
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SetPciConfigSpace(pa, CFGSPACE_BRIDGE_CTRL, &wData, sizeof(wData));
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}
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else if ((pa->bDevType == DEVTYPE_CL_PD6834) ||
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(pa->bDevType == DEVTYPE_CL_PD6833))
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{
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//enable CSC IRQ routing just for IRQ detection
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GetPciConfigSpace(pa, CFGSPACE_CL_CFGMISC1, &bData, sizeof(bData));
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bData |= CL_CFGMISC1_ISACSC;
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SetPciConfigSpace(pa, CFGSPACE_CL_CFGMISC1, &bData, sizeof(bData));
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}
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else if ((pa->bDevType == DEVTYPE_TI_PCI1130) ||
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(pa->bDevType == DEVTYPE_TI_PCI1131) ||
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(pa->bDevType == DEVTYPE_TI_PCI1031))
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{
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GetPciConfigSpace(pa, CFGSPACE_TI_DEV_CTRL, &wData, sizeof(wData));
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if ((wData & DEVCTRL_INTMODE_MASK) == DEVCTRL_INTMODE_COMPAQ)
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{
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//
|
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// There is an errata on TI 1130, 1131 and 1031 in which if
|
|
// the chip is programmed to use serial IRQ mode (i.e. COMPAQ
|
|
// mode) and the SERIRQ pin is not pull up with a 1K resistor,
|
|
// the SERIRQ line will rise too slowly after IRQ 15 is
|
|
// deasserted so that it looks like NMI should be asserted.
|
|
// This caused spurious NMI. This is a hardware problem.
|
|
// Unfortunately, there are a large number of machines with
|
|
// this problem on the street already, so CBSS has to work
|
|
// around the problem by temporarily disabling NMI before
|
|
// doing ISA IRQ detection.
|
|
//
|
|
fTINMIBug = TRUE;
|
|
_asm in al,SYSCTRL_B
|
|
_asm and al,0x0f
|
|
_asm push ax
|
|
//
|
|
// Mask NMI
|
|
//
|
|
_asm or al,0x08
|
|
_asm out SYSCTRL_B,al
|
|
}
|
|
}
|
|
_asm pushf
|
|
_asm cli //disable interrupt
|
|
_asm in al,PIC2_IMR //save old IMRs
|
|
_asm mov ah,al
|
|
_asm in al,PIC1_IMR
|
|
_asm push ax
|
|
|
|
_asm mov al,0xff //mask all interrupt
|
|
_asm out PIC2_IMR,al
|
|
_asm out PIC1_IMR,al
|
|
|
|
for (i = 0; i < 16; ++i)
|
|
{
|
|
w = (USHORT)(1 << i);
|
|
if ((pa->wValidIRQs & w) &&
|
|
((wIRQMask = ToggleIRQLine(pa, i)) != 0))
|
|
{
|
|
_asm mov dx, wIRQMask
|
|
_asm _emit 0x66
|
|
_asm _emit 0x0f
|
|
_asm _emit 0xbc
|
|
_asm _emit 0xc2
|
|
_asm mov wRealIRQ,ax
|
|
pa->abIRQMap[wRealIRQ] = i;
|
|
wRealIRQMask |= (USHORT)(1 << wRealIRQ);
|
|
}
|
|
}
|
|
Clear_IR_Bits(wRealIRQMask);
|
|
|
|
_asm pop ax
|
|
_asm out PIC1_IMR,al
|
|
_asm mov al,ah
|
|
_asm out PIC2_IMR,al
|
|
_asm popf
|
|
|
|
if (fTINMIBug)
|
|
{
|
|
//
|
|
// Restore NMI mask
|
|
//
|
|
_asm pop ax
|
|
_asm out SYSCTRL_B,al
|
|
}
|
|
|
|
if (pa->bDevType == DEVTYPE_CL_PD6832)
|
|
{
|
|
//disable CSC IRQ routing (use PCI interrupt for CSC)
|
|
GetPciConfigSpace(pa, CFGSPACE_BRIDGE_CTRL, &wData, sizeof(wData));
|
|
wData &= ~BCTRL_CL_CSCIRQROUTING_ENABLE;
|
|
SetPciConfigSpace(pa, CFGSPACE_BRIDGE_CTRL, &wData, sizeof(wData));
|
|
}
|
|
else if ((pa->bDevType == DEVTYPE_CL_PD6834) ||
|
|
(pa->bDevType == DEVTYPE_CL_PD6833))
|
|
{
|
|
//disable CSC IRQ routing (use PCI interrupt for CSC)
|
|
GetPciConfigSpace(pa, CFGSPACE_CL_CFGMISC1, &bData, sizeof(bData));
|
|
bData &= ~CL_CFGMISC1_ISACSC;
|
|
SetPciConfigSpace(pa, CFGSPACE_CL_CFGMISC1, &bData, sizeof(bData));
|
|
}
|
|
|
|
return wRealIRQMask;
|
|
} //DetectIRQMap
|
|
|
|
|
|
|
|
USHORT
|
|
ToggleIRQLine(
|
|
PPCCARD_INFORMATION pa,
|
|
UCHAR bIRQ
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This routine toggles the specified IRQ line from the adapter.
|
|
|
|
Arguments:
|
|
|
|
pa -> ADAPTER structure
|
|
bIRQ - IRQ line to toggle
|
|
|
|
Returns:
|
|
|
|
returns the IRR mask from PIC
|
|
|
|
--*/
|
|
{
|
|
UCHAR bOldIntCtrl, bOldIntCfg, bData;
|
|
USHORT rc = 0, irr1, irr2, irr3;
|
|
|
|
bOldIntCfg = PcicReadSocket(pa, EXCAREG_CSC_CFG);
|
|
bOldIntCtrl = PcicReadSocket(pa, EXCAREG_INT_GENCTRL);
|
|
|
|
//Set to a known state
|
|
PcicWriteSocket(pa, EXCAREG_INT_GENCTRL, IGC_PCCARD_RESETLO);
|
|
|
|
//Set irq number in interrupt control register and enable irq
|
|
PcicWriteSocket(pa, EXCAREG_CSC_CFG, (UCHAR)((bIRQ << 4) | CSCFG_CD_ENABLE));
|
|
|
|
//clear all pending interrupts
|
|
bData = PcicReadSocket(pa, EXCAREG_CARD_STATUS);
|
|
irr1 = GetPICIRR();
|
|
|
|
if (PcicReadSocket(pa, EXCAREG_IDREV) != 0x82)
|
|
{
|
|
//This is not an A stepping part, try the undocumented interrupt
|
|
//register. If this fails the other routine will be tried.
|
|
PcicWriteSocket(pa, EXCAREG_CARDDET_GENCTRL, CDGC_SW_DET_INT);
|
|
irr2 = GetPICIRR();
|
|
|
|
//reset pending interrupt
|
|
bData = PcicReadSocket(pa, EXCAREG_CARD_STATUS);
|
|
irr3 = GetPICIRR();
|
|
rc = (USHORT)((irr1 ^ irr2) & (irr2 ^ irr3));
|
|
}
|
|
|
|
if (rc == 0)
|
|
{
|
|
//Generate interrupt by de-asserting IRQ line so the PIC can pull it
|
|
//high
|
|
PcicWriteSocket(pa, EXCAREG_CSC_CFG, 0);
|
|
//if (pa->dwfAdapter & AF_TI_SERIALIRQ)
|
|
// TIReleaseSerialIRQ(pa, bIRQ);
|
|
irr2 = GetPICIRR();
|
|
|
|
//re-assert IRQ line
|
|
PcicWriteSocket(pa, EXCAREG_CSC_CFG, (UCHAR)((bIRQ << 4) | CSCFG_CD_ENABLE));
|
|
|
|
//reset pending interrupt
|
|
bData = PcicReadSocket(pa, EXCAREG_CARD_STATUS);
|
|
irr3 = GetPICIRR();
|
|
rc = (USHORT)((irr1 ^ irr2) & (irr2 ^ irr3));
|
|
}
|
|
|
|
PcicWriteSocket(pa, EXCAREG_CSC_CFG, bOldIntCfg);
|
|
PcicWriteSocket(pa, EXCAREG_INT_GENCTRL, bOldIntCtrl);
|
|
|
|
return rc;
|
|
} //ToggleIRQLine
|
|
|
|
|
|
/***LP GetPICIRR - Read PIC IRR
|
|
*
|
|
* ENTRY
|
|
* None
|
|
*
|
|
* EXIT
|
|
* returns the IRR mask from PIC
|
|
*/
|
|
|
|
USHORT GetPICIRR(VOID)
|
|
{
|
|
USHORT wData;
|
|
|
|
//
|
|
// Delay 2 usec before reading PIC because serial IRQ may be a bit slow.
|
|
//
|
|
TimeOut(4);
|
|
|
|
_asm mov al,PIC_RD_IR
|
|
_asm out PIC2_OCW3,al
|
|
_asm in al,PIC2_OCW3
|
|
_asm mov ah,al
|
|
|
|
_asm mov al,PIC_RD_IR
|
|
_asm out PIC1_OCW3,al
|
|
_asm in al,PIC1_OCW3
|
|
|
|
_asm mov wData,ax
|
|
|
|
return wData;
|
|
} //GetPICIRR
|
|
|
|
|
|
|
|
UCHAR
|
|
PcicReadSocket(
|
|
PPCCARD_INFORMATION pa,
|
|
USHORT Reg
|
|
)
|
|
{
|
|
USHORT IoBase = pa->IoBase;
|
|
UCHAR value;
|
|
_asm {
|
|
mov dx, IoBase
|
|
mov ax, Reg
|
|
out dx, al
|
|
inc dx
|
|
in al, dx
|
|
mov value, al
|
|
}
|
|
return value;
|
|
}
|
|
|
|
VOID
|
|
PcicWriteSocket(
|
|
PPCCARD_INFORMATION pa,
|
|
USHORT Reg,
|
|
UCHAR value
|
|
)
|
|
{
|
|
USHORT IoBase = pa->IoBase;
|
|
_asm {
|
|
mov dx, IoBase
|
|
mov ax, Reg
|
|
out dx, al
|
|
inc dx
|
|
mov al, value
|
|
out dx, al
|
|
}
|
|
}
|
|
|
|
|
|
UCHAR PCIDeref[4][4] = { {4,1,2,2},{1,1,1,1},{2,1,2,2},{1,1,1,1} };
|
|
|
|
VOID
|
|
SetPciConfigSpace(
|
|
PPCCARD_INFORMATION pa,
|
|
USHORT Offset,
|
|
PVOID pvBuffer,
|
|
USHORT Length
|
|
)
|
|
|
|
{
|
|
USHORT IoSize;
|
|
PUCHAR Buffer = (PUCHAR) pvBuffer;
|
|
//
|
|
// Read it
|
|
//
|
|
while (Length) {
|
|
pa->PciCfg1.u.bits.RegisterNumber = Offset / sizeof(ULONG);
|
|
|
|
IoSize = PCIDeref[Offset % sizeof(ULONG)][Length % sizeof(ULONG)];
|
|
|
|
SetPCIType1Data (pa->PciCfg1.u.AsULONG,
|
|
(Offset % sizeof(ULONG)),
|
|
Buffer,
|
|
IoSize);
|
|
|
|
Offset += IoSize;
|
|
Buffer += IoSize;
|
|
Length -= IoSize;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
VOID
|
|
GetPciConfigSpace(
|
|
PPCCARD_INFORMATION pa,
|
|
USHORT Offset,
|
|
PVOID pvBuffer,
|
|
USHORT Length
|
|
)
|
|
{
|
|
USHORT IoSize;
|
|
USHORT i;
|
|
PUCHAR Buffer = (PUCHAR) pvBuffer;
|
|
|
|
//
|
|
// Zap input buffer
|
|
//
|
|
|
|
for (i=0; i < Length; i++) {
|
|
Buffer[i] = 0xff;
|
|
}
|
|
|
|
//
|
|
// Read it
|
|
//
|
|
while (Length) {
|
|
pa->PciCfg1.u.bits.RegisterNumber = Offset / sizeof(ULONG);
|
|
|
|
IoSize = PCIDeref[Offset % sizeof(ULONG)][Length % sizeof(ULONG)];
|
|
|
|
GetPCIType1Data (pa->PciCfg1.u.AsULONG,
|
|
(Offset % sizeof(ULONG)),
|
|
Buffer,
|
|
IoSize);
|
|
|
|
Offset += IoSize;
|
|
Buffer += IoSize;
|
|
Length -= IoSize;
|
|
}
|
|
}
|
|
|