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1133 lines
22 KiB
1133 lines
22 KiB
/*++
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Copyright (c) 2000 Microsoft Corporation
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Module Name:
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mpipi.c
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Abstract:
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This module provides the HAL support for interprocessor interrupts and
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processor initialization for MPS systems.
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Author:
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Forrest Foltz (forrestf) 27-Oct-2000
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Environment:
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Kernel mode only.
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Revision History:
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--*/
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#include "halcmn.h"
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#define HAL_FORCEINLINE __forceinline
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//
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// External functions
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//
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VOID
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HalpResetThisProcessor (
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VOID
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);
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ULONG
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DetectAcpiMP (
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OUT PBOOLEAN IsConfiguredMp,
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IN PLOADER_PARAMETER_BLOCK LoaderBlock
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);
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//
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// External data
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//
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extern KAFFINITY HalpNodeAffinity[];
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extern INTERRUPT_DEST HalpIpiDestinationMap[sizeof(KAFFINITY)][256];
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extern BOOLEAN HalpStaticIntAffinity;
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extern UCHAR rgzBadHal[];
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//
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// Local types
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//
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typedef
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VOID
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(*HAL_GENERIC_IPI_FUNCTION) (
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ULONG_PTR Context
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);
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//
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// Local prototypes
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//
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VOID
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HalInitApicInterruptHandlers(
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VOID
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);
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//
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// External data
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//
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extern UCHAR HalpPICINTToVector[16];
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//
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// Local data and defines
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//
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KSPIN_LOCK HalpBroadcastLock;
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KAFFINITY volatile HalpBroadcastTargets;
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ULONG_PTR HalpBroadcastContext;
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HAL_GENERIC_IPI_FUNCTION HalpBroadcastFunction;
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PKPCR HalpProcessorPCR[MAXIMUM_PROCESSORS];
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//
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// HalpGlobal8259Mask is used to avoid reading the PIC to get the current
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// interrupt mask; format is the same as for SET_8259_MASK, i.i.,
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// bits 7:0 -> PIC1, 15:8 -> PIC2
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//
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USHORT HalpGlobal8259Mask = 0;
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#define GENERIC_IPI (DELIVER_FIXED | LOGICAL_DESTINATION | ICR_USE_DEST_FIELD | APIC_GENERIC_VECTOR)
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#define APIC_IPI (DELIVER_FIXED | LOGICAL_DESTINATION | ICR_USE_DEST_FIELD | APIC_IPI_VECTOR)
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//
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// Globals and constants used to log local apic errors
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//
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#define LogApicErrors TRUE
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#if LogApicErrors
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//
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// Structure defining the layout of an apic error record.
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//
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typedef struct _APIC_ERROR {
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union {
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struct {
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UCHAR SendChecksum:1;
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UCHAR ReceiveChecksum:1;
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UCHAR SendAccept:1;
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UCHAR ReceiveAccept:1;
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UCHAR Reserved1:1;
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UCHAR SendVector:1;
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UCHAR ReceiveVector:1;
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UCHAR RegisterAddress:1;
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};
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UCHAR AsByte;
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};
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UCHAR Processor;
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} APIC_ERROR, *PAPIC_ERROR;
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#define APIC_ERROR_LOG_SIZE 128
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//
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// Count of local apic errors.
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//
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ULONG HalpLocalApicErrorCount = 0;
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//
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// Apic error log. This is circular, indexed by
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// HalpLocalApicErrorCount % APIC_ERROR_LOG_SIZE.
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//
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APIC_ERROR HalpApicErrorLog[APIC_ERROR_LOG_SIZE];
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//
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// Spinlock used to protect access to HalpLocalApicErrorCount.
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//
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KSPIN_LOCK HalpLocalApicErrorLock;
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#endif
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HAL_FORCEINLINE
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VOID
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HalpSendIpiWorker (
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IN UCHAR TargetSet,
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IN ULONG Command
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)
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/*++
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Routine Description:
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This routine is called to send an IPI command to a set of processors
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on a single node.
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Parameters:
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TargetSet - Specifies the processor identifiers within the node.
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Command - Specifies the IPI command to send.
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Return Value:
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None.
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--*/
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{
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ULONG destination;
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//
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// Only high byte of the destination is used. Wait until the Apic is
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// not busy before sending. Continue without waiting, there will be
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// another wait after all IPIs have been submitted.
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//
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destination = (ULONG)TargetSet << DESTINATION_SHIFT;
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HalpStallWhileApicBusy();
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LOCAL_APIC(LU_INT_CMD_HIGH) = destination;
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LOCAL_APIC(LU_INT_CMD_LOW) = Command;
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}
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HAL_FORCEINLINE
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VOID
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HalpSendNodeIpi (
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IN KAFFINITY Affinity,
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IN ULONG Command
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)
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/*++
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Routine Description:
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Parameters:
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Affinity - Specifies the set of processors to receive the IPI.
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Command - Specifies the IPI command to send.
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Return Value:
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None.
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--*/
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{
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KAFFINITY remainingProcessors;
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PKAFFINITY nodeAffinity;
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ULONG chunkNo;
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INTERRUPT_DEST intDest;
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INTERRUPT_DEST intDestSum;
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UCHAR affinityChunk;
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//
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// Declare a local union that can be used to access an affinity
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// both chunk-wise and as a whole.
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//
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union {
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UCHAR Chunks[sizeof(KAFFINITY)];
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KAFFINITY Whole;
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} affinity;
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//
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// Affinity has some number of target processors indicated. Each
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// target processor is a member of a cluster of processors, or "node".
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//
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// For each node, determine whether it contains any of the target
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// processors. If so, send an IPI command targeting those processors
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// and send it to the node.
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//
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nodeAffinity = HalpNodeAffinity;
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remainingProcessors = Affinity & HalpActiveProcessors;
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while (remainingProcessors != 0) {
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//
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// Iterate through the node affinities here until a node containing
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// at least some of the targeted processors is encountered.
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//
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do {
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//
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// Determine the set of target CPUs that can be found in this
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// node.
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//
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affinity.Whole = *nodeAffinity & remainingProcessors;
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//
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// Point nodeAffinity at the affinity for the next cluster.
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//
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nodeAffinity += 1;
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ASSERT((nodeAffinity - HalpNodeAffinity) < MAX_NODES);
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} while (affinity.Whole == 0);
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//
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// Remove the processors that will be processed on this node from
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// the set of processors remaining to be processed.
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//
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remainingProcessors ^= affinity.Whole;
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//
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// Accumulate the logical target mask
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//
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intDestSum.LogicalId = 0;
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chunkNo = 0;
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do {
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//
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// Isolate a chunk of the processor affinity mask.
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//
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affinityChunk = affinity.Chunks[chunkNo];
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//
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// Use that chunk as an index into HalpIpiDestinationMap[][],
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// retrieving the logical sum of all node/processor IDs that
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// are associated with each bit that is set in that affinity
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// chunk.
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//
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intDest = HalpIpiDestinationMap[chunkNo][affinityChunk];
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//
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// Now, sum it with the logical ID mask that is being accumulated
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// for each affinity chunk.
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//
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intDestSum.LogicalId |= intDest.LogicalId;
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//
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// Indicate that the processors represented in this chunk
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// have been processed. When there are no more processors
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// left to process for this node, send the IPI and proceed
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// to the next node.
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//
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affinity.Chunks[chunkNo] = 0;
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chunkNo += 1;
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} while (affinity.Whole != 0);
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//
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// intDest contains an accumulated set of hardware processor
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// identifiers, representing all of the processors on this node that
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// should receive the command.
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//
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HalpSendIpiWorker(intDestSum.LogicalId,Command);
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}
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}
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VOID
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HalpSendIpi (
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IN KAFFINITY Affinity,
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IN ULONG Command
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)
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/*++
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Routine Description:
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Affinity - Specifies the set of processors to receive the IPI.
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Command - Specifies the IPI command to send.
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Parameters:
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None.
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Return Value:
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None.
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--*/
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{
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ULONG flags;
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//
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// Disable interrupts and call the appropriate routine.
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//
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flags = HalpDisableInterrupts();
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if (HalpMaxProcsPerCluster == 0) {
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//
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// We know that the maximum number of processors is 8,
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// so send the IPI directly.
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//
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ASSERT((Affinity & 0xFF) == Affinity);
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HalpSendIpiWorker((UCHAR)Affinity,Command);
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} else {
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//
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// Send an IPI to one or mode nodes.
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//
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HalpSendNodeIpi(Affinity,Command);
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}
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//
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// Stall until the last IPI has been sent, restore interrupts and
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// return.
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//
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HalpStallWhileApicBusy();
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HalpRestoreInterrupts(flags);
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}
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VOID
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HalInitializeProcessor(
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ULONG ProcessorNumber,
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PLOADER_PARAMETER_BLOCK LoaderBlock
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)
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/*++
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Routine Description:
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Initialize hal pcr values for current processor (if any)
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(called shortly after processor reaches kernel, before
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HalInitSystem if P0)
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IPI's and KeReadir/LowerIrq's must be available once this function
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returns. (IPI's are only used once two or more processors are
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available)
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. Enable IPI interrupt (makes sense for P1, P2, ...).
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. Save Processor Number in PCR.
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. if (P0)
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. determine if the system is a PC+MP,
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. if not a PC+MP System Halt;
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. Enable IPI's on CPU.
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Arguments:
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Number - Logical processor number of calling processor
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Return Value:
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None.
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--*/
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{
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PKPCR pcr;
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KAFFINITY affinity;
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KAFFINITY oldAffinity;
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ULONG detectAcpiResult;
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BOOLEAN isMp;
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affinity = (KAFFINITY)1 << ProcessorNumber;
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pcr = KeGetPcr();
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//
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// Mark all interrupts as disabled, and store the processor number and
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// the default stall scale factor in the pcr.
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//
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pcr->Idr = 0xFFFFFFFF;
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pcr->Number = (UCHAR)ProcessorNumber;
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pcr->StallScaleFactor = INITIAL_STALL_COUNT;
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//
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// Record the pcr pointer in our lookup table and set the affinity
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// bit in our set of active processors.
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//
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HalpProcessorPCR[ProcessorNumber] = pcr;
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HalpActiveProcessors |= affinity;
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if (HalpStaticIntAffinity == 0) {
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//
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// Interrupts can go to any processor
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//
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HalpDefaultInterruptAffinity |= affinity;
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} else {
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//
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// Interrupts go only to the highest numbered processor
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//
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if (HalpDefaultInterruptAffinity < affinity) {
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HalpDefaultInterruptAffinity = affinity;
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}
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}
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if (ProcessorNumber == 0) {
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KeInitializeSpinLock(&HalpBroadcastLock);
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#if LogApicErrors
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KeInitializeSpinLock(&HalpLocalApicErrorLock);
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#endif
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//
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// Determine whether the system we are on is an MPS system.
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//
|
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// DetectMPS has a parameter we don't currently use. It's a boolean
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// which is set to TRUE if the system we're on is an MP system.
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// We could have a UP MPS system.
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//
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// The DetectMPS routine also allocates virtual addresses for all of
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// the APICs in the system.
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//
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#if defined(ACPI_HAL)
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detectAcpiResult = DetectAcpiMP(&isMp,LoaderBlock);
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#else
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detectAcpiResult = DetectMPS(&isMp);
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#endif
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if (detectAcpiResult == FALSE) {
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HalDisplayString(rgzBadHal);
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HalpDisableInterrupts();
|
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while (TRUE) {
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HalpHalt();
|
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}
|
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}
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HalpRegisterKdSupportFunctions(LoaderBlock);
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//
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// Mask all PIC interrupts
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//
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HalpGlobal8259Mask = 0xFFFF;
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SET_8259_MASK(HalpGlobal8259Mask);
|
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}
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//
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// All processors execute this code
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//
|
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HalInitApicInterruptHandlers();
|
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HalpInitializeLocalUnit();
|
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}
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VOID
|
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HalInitApicInterruptHandlers(
|
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VOID
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)
|
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|
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/*++
|
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|
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Routine Description:
|
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This routine installs the interrupt vector in the IDT for the APIC
|
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spurious interrupt.
|
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Arguments:
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None.
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Return Value:
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None.
|
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--*/
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{
|
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PKPCR pcr;
|
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PKIDTENTRY64 idt;
|
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|
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KiSetHandlerAddressToIDTIrql(PIC1_SPURIOUS_VECTOR,
|
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PicSpuriousService37,
|
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NULL,
|
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0);
|
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|
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KiSetHandlerAddressToIDTIrql(APIC_SPURIOUS_VECTOR,
|
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HalpApicSpuriousService,
|
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NULL,
|
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0);
|
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}
|
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|
|
__forceinline
|
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VOID
|
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HalpPollForBroadcast (
|
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VOID
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Checks whether the current processor has a broadcast function pending
|
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and, if so, clears it's pending bit and calls the function.
|
|
|
|
Arguments:
|
|
|
|
None.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
|
|
{
|
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KAFFINITY affinity;
|
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ULONG_PTR broadcastContext;
|
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HAL_GENERIC_IPI_FUNCTION broadcastFunction;
|
|
KAFFINITY broadcastTargets;
|
|
|
|
affinity = KeGetPcr()->CurrentPrcb->SetMember;
|
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if ((HalpBroadcastTargets & affinity) != 0) {
|
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|
|
//
|
|
// A pending generic IPI call appears to be pending for this
|
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// processor. Pick up the function pointer and context locally.
|
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//
|
|
|
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broadcastFunction = HalpBroadcastFunction;
|
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broadcastContext = HalpBroadcastContext;
|
|
|
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//
|
|
// Atomically acknowledge the broadcast. If the broadcast is still
|
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// pending for this processor, then call it.
|
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//
|
|
|
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// BUGBUG
|
|
// broadcastTargets = InterlockedAnd64(&HalpBroadcastTargets,~affinity);
|
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broadcastTargets &= ~affinity;
|
|
if ((broadcastTargets & affinity) != 0) {
|
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broadcastFunction(broadcastContext);
|
|
}
|
|
}
|
|
}
|
|
|
|
VOID
|
|
HalpGenericCall(
|
|
IN HAL_GENERIC_IPI_FUNCTION BroadcastFunction,
|
|
IN ULONG Context,
|
|
IN KAFFINITY TargetProcessors
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Causes the WorkerFunction to be called on the specified target
|
|
processors. The WorkerFunction is called at CLOCK2_LEVEL-1
|
|
(Must be below IPI_LEVEL in order to prevent system deadlocks).
|
|
|
|
Enviroment:
|
|
|
|
Must be called with interrupts enabled.
|
|
Must be called with IRQL = CLOCK2_LEVEL-1
|
|
|
|
--*/
|
|
|
|
{
|
|
//
|
|
// Nothing to do if no target processors have been specified.
|
|
//
|
|
|
|
if (TargetProcessors == 0) {
|
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return;
|
|
}
|
|
|
|
//
|
|
// Acquire the broadcast lock, polling for broadcasts while spinning.
|
|
//
|
|
|
|
while (KeTryToAcquireSpinLockAtDpcLevel(&HalpBroadcastLock) == FALSE) {
|
|
do {
|
|
HalpPollForBroadcast();
|
|
} while (KeTestSpinLock(&HalpBroadcastLock) == FALSE);
|
|
}
|
|
|
|
//
|
|
// We own the broadcast lock. Store the broadcast parameters
|
|
// into the broadcast prameters and send the generic IPI.
|
|
//
|
|
|
|
HalpBroadcastFunction = BroadcastFunction;
|
|
HalpBroadcastContext = Context;
|
|
HalpBroadcastTargets = TargetProcessors;
|
|
HalpSendIpi(TargetProcessors,GENERIC_IPI);
|
|
|
|
//
|
|
// Wait for all processors to pick up the IPI and process the generic
|
|
// call, then release the broadcast lock.
|
|
//
|
|
|
|
do {
|
|
HalpPollForBroadcast();
|
|
} while (HalpBroadcastTargets != 0);
|
|
|
|
KeReleaseSpinLockFromDpcLevel(&HalpBroadcastLock);
|
|
}
|
|
|
|
|
|
ULONG
|
|
HalpWaitForPending (
|
|
IN ULONG Count,
|
|
IN ULONG volatile *ICR
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Spins waiting for the DELIVERY_PENDING bit in the ICR to clear or
|
|
until spinning Count times.
|
|
|
|
Arguments:
|
|
|
|
Count - Number of times through the loop before giving up.
|
|
|
|
ICR - Pointer to the ICR register containing the DELIVERY_PENDING
|
|
status bit.
|
|
|
|
Return Value:
|
|
|
|
Zero if the DELIVERY_PENDING bit has cleared within the number of
|
|
test cycles, non-zero otherwise.
|
|
|
|
--*/
|
|
|
|
{
|
|
ULONG countRemaining;
|
|
|
|
countRemaining = Count;
|
|
while (countRemaining > 0) {
|
|
|
|
if ((*ICR & DELIVERY_PENDING) != 0) {
|
|
break;
|
|
}
|
|
countRemaining -= 1;
|
|
}
|
|
|
|
return countRemaining;
|
|
}
|
|
|
|
VOID
|
|
HalRequestIpi (
|
|
IN KAFFINITY Affinity
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Requests an interprocessor interrupt
|
|
|
|
Arguments:
|
|
|
|
Affinity - Supplies the set of processors to be interrupted
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
|
|
{
|
|
HalpSendIpi(Affinity,APIC_IPI);
|
|
}
|
|
|
|
BOOLEAN
|
|
HalpApicRebootService (
|
|
IN PKINTERRUPT Interrupt,
|
|
IN PVOID ServiceContext
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This is the ISR that handles Reboot interrupts.
|
|
|
|
Arguments:
|
|
|
|
Interrupt - Supplies a pointer to the kernel interrupt object
|
|
|
|
ServiceContext - Supplies the service context
|
|
|
|
Return Value:
|
|
|
|
None. This routine does not return.
|
|
|
|
--*/
|
|
|
|
{
|
|
UNREFERENCED_PARAMETER(Interrupt);
|
|
UNREFERENCED_PARAMETER(ServiceContext);
|
|
|
|
LOCAL_APIC(LU_TPR) = APIC_REBOOT_VECTOR;
|
|
|
|
//
|
|
// EOI the local APIC. Warm reset does not reset the 82489 APIC
|
|
// so if we don't EOI here we'll never see an interrupt after the
|
|
// reboot.
|
|
//
|
|
|
|
LOCAL_APIC(LU_EOI) = 0;
|
|
|
|
//
|
|
// Reset this processor. This function will not return.
|
|
//
|
|
|
|
HalpResetThisProcessor();
|
|
ASSERT(FALSE);
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
|
|
BOOLEAN
|
|
HalpBroadcastCallService (
|
|
IN PKINTERRUPT Interrupt,
|
|
IN PVOID ServiceContext
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This is the ISR that handles broadcast call interrupts.
|
|
|
|
Arguments:
|
|
|
|
Interrupt - Supplies a pointer to the kernel interrupt object
|
|
|
|
ServiceContext - Supplies the service context
|
|
|
|
Return Value:
|
|
|
|
TRUE
|
|
|
|
--*/
|
|
|
|
{
|
|
UNREFERENCED_PARAMETER(Interrupt);
|
|
UNREFERENCED_PARAMETER(ServiceContext);
|
|
|
|
HalpPollForBroadcast();
|
|
return TRUE;
|
|
}
|
|
|
|
BOOLEAN
|
|
HalpIpiHandler (
|
|
IN PKINTERRUPT Interrupt,
|
|
IN PVOID ServiceContext
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This routine is entered as the result of an interrupt generated by
|
|
interprocessor communication.
|
|
|
|
Arguments:
|
|
|
|
Interrupt - Supplies a pointer to the kernel interrupt object
|
|
|
|
ServiceContext - Supplies the service context
|
|
|
|
Return Value:
|
|
|
|
TRUE
|
|
|
|
--*/
|
|
|
|
{
|
|
UNREFERENCED_PARAMETER(Interrupt);
|
|
|
|
KiIpiServiceRoutine(Interrupt->TrapFrame,NULL);
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
BOOLEAN
|
|
HalpLocalApicErrorService (
|
|
IN PKINTERRUPT Interrupt,
|
|
IN PVOID ServiceContext
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This routine is entered as the result of an interrupt generated by
|
|
a local apic error. It clears the error and, if apic error logging
|
|
is turned on, records information about the error.
|
|
|
|
Arguments:
|
|
|
|
Interrupt - Supplies a pointer to the kernel interrupt object
|
|
|
|
ServiceContext - Supplies the service context
|
|
|
|
Return Value:
|
|
|
|
TRUE
|
|
|
|
--*/
|
|
|
|
{
|
|
ULONG flags;
|
|
PAPIC_ERROR apicError;
|
|
ULONG index;
|
|
ULONG errorStatus;
|
|
PKPCR pcr;
|
|
|
|
#if LogApicErrors
|
|
|
|
//
|
|
// Take the apic error log lock, get a pointer to the next available
|
|
// error log slot, and increment the error count.
|
|
//
|
|
|
|
flags = HalpAcquireHighLevelLock(&HalpLocalApicErrorLock);
|
|
|
|
index = HalpLocalApicErrorCount % APIC_ERROR_LOG_SIZE;
|
|
apicError = &HalpApicErrorLog[index];
|
|
HalpLocalApicErrorCount += 1;
|
|
|
|
#endif
|
|
|
|
//
|
|
// The Apic EDS (Rev 4.0) says you have to write before you read.
|
|
// This doesn't work. The write clears the status bits, but the P6 works
|
|
// according to the EDS.
|
|
//
|
|
// For AMD64, for now assume that things work according to the EDS spec.
|
|
//
|
|
|
|
LOCAL_APIC(LU_ERROR_STATUS) = 0;
|
|
errorStatus = LOCAL_APIC(LU_ERROR_STATUS);
|
|
|
|
#if LogApicErrors
|
|
|
|
//
|
|
// Fill in the error log and release the apic error log lock.
|
|
//
|
|
|
|
pcr = KeGetPcr();
|
|
apicError->AsByte = (UCHAR)errorStatus;
|
|
apicError->Processor = pcr->Number;
|
|
|
|
HalpReleaseHighLevelLock(&HalpLocalApicErrorLock,flags);
|
|
|
|
#endif
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
|
|
BOOLEAN
|
|
PicNopHandlerInt (
|
|
IN PKINTERRUPT Interrupt,
|
|
IN PVOID Context
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This handler is designed to be installed on a system to field any PIC
|
|
interrupts when there are not supposed to be any delivered.
|
|
|
|
This routine EOIs the PIC and returns.
|
|
|
|
Arguments:
|
|
|
|
Interrupt - Supplies a pointer to the kernel interrupt object
|
|
|
|
ServiceContext - Supplies the service context
|
|
|
|
Return Value:
|
|
|
|
TRUE
|
|
|
|
--*/
|
|
|
|
{
|
|
UCHAR irq;
|
|
|
|
AMD64_COVERAGE_TRAP();
|
|
|
|
//
|
|
// Context is the PIC IRQ
|
|
//
|
|
|
|
ASSERT((ULONG_PTR)Context <= 15);
|
|
|
|
irq = (UCHAR)(ULONG_PTR)(Context);
|
|
if (irq <= 7) {
|
|
|
|
WRITE_PORT_UCHAR(PIC1_PORT0,irq | OCW2_SPECIFIC_EOI);
|
|
|
|
} else {
|
|
|
|
if (irq == 0x0D) {
|
|
WRITE_PORT_UCHAR(I386_80387_BUSY_PORT, 0);
|
|
}
|
|
|
|
WRITE_PORT_UCHAR(PIC2_PORT0,OCW2_NON_SPECIFIC_EOI);
|
|
WRITE_PORT_UCHAR(PIC1_PORT0,OCW2_SPECIFIC_EOI | PIC_SLAVE_IRQ);
|
|
}
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
|
|
BOOLEAN
|
|
PicInterruptHandlerInt (
|
|
IN PKINTERRUPT Interrupt,
|
|
IN PVOID Context
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
These handlers receive interrupts from the PIC and reissues them via a
|
|
vector at the proper priority level. This is used to provide a symetric
|
|
interrupt distribution on a non symetric system.
|
|
|
|
The PIC interrupts will normally only be received (in the PC+MP Hal) via
|
|
an interrupt input from on either the IO Unit or the Local unit which has
|
|
been programed as EXTINT. EXTINT interrupts are received outside of the
|
|
APIC priority structure (the PIC provides the vector). We use the APIC
|
|
ICR to generate interrupts to the proper handler at the proper priority.
|
|
|
|
The EXTINT interrupts are directed to a single processor, currently P0.
|
|
There is no good reason why they can't be directed to another processor.
|
|
|
|
Since one processor must absorb the overhead of redistributing PIC
|
|
interrupts the interrupt handling on a system using EXTINT interrupts is
|
|
not symetric.
|
|
|
|
Arguments:
|
|
|
|
Interrupt - Supplies a pointer to the kernel interrupt object
|
|
|
|
ServiceContext - Supplies the service context
|
|
|
|
Return Value:
|
|
|
|
TRUE
|
|
|
|
--*/
|
|
|
|
{
|
|
UCHAR irq;
|
|
UCHAR isrRegister;
|
|
UCHAR ipiVector;
|
|
|
|
AMD64_COVERAGE_TRAP();
|
|
|
|
//
|
|
// Context is the PIC IRQ
|
|
//
|
|
|
|
ASSERT((ULONG_PTR)Context <= 15);
|
|
|
|
irq = (UCHAR)(ULONG_PTR)(Context);
|
|
if (irq == 7) {
|
|
|
|
//
|
|
// Check to see if this is a spurious interrupt
|
|
//
|
|
|
|
WRITE_PORT_UCHAR(PIC1_PORT0,OCW3_READ_ISR);
|
|
IO_DELAY();
|
|
isrRegister = READ_PORT_UCHAR(PIC1_PORT0);
|
|
if ((isrRegister & 0x80) == 0) {
|
|
|
|
//
|
|
// Spurious.
|
|
//
|
|
|
|
return TRUE;
|
|
}
|
|
}
|
|
|
|
if (irq == 0x0D) {
|
|
|
|
WRITE_PORT_UCHAR(I386_80387_BUSY_PORT,0);
|
|
|
|
} else if (irq == 0x1F) {
|
|
|
|
WRITE_PORT_UCHAR(PIC2_PORT0,OCW3_READ_ISR);
|
|
IO_DELAY();
|
|
isrRegister = READ_PORT_UCHAR(PIC2_PORT0);
|
|
if ((isrRegister & 0x80) == 0) {
|
|
|
|
//
|
|
// Spurious.
|
|
//
|
|
|
|
return TRUE;
|
|
}
|
|
}
|
|
|
|
if (irq <= 7) {
|
|
|
|
//
|
|
// Master PIC
|
|
//
|
|
|
|
WRITE_PORT_UCHAR(PIC1_PORT0,irq | OCW2_SPECIFIC_EOI);
|
|
|
|
} else {
|
|
|
|
//
|
|
// Slave PIC
|
|
//
|
|
|
|
WRITE_PORT_UCHAR(PIC2_PORT0,OCW2_NON_SPECIFIC_EOI);
|
|
WRITE_PORT_UCHAR(PIC1_PORT0,OCW2_SPECIFIC_EOI | PIC_SLAVE_IRQ);
|
|
}
|
|
|
|
ipiVector = HalpPICINTToVector[irq];
|
|
|
|
if (ipiVector != 0) {
|
|
|
|
HalpStallWhileApicBusy();
|
|
if (irq == 8) {
|
|
|
|
//
|
|
// Clock interrupt
|
|
//
|
|
|
|
LOCAL_APIC(LU_INT_CMD_LOW) =
|
|
DELIVER_FIXED | ICR_SELF | APIC_CLOCK_VECTOR;
|
|
|
|
} else {
|
|
|
|
//
|
|
// Write the IPI command to the Memory Mapped Register
|
|
//
|
|
|
|
LOCAL_APIC(LU_INT_CMD_HIGH) = DESTINATION_ALL_CPUS;
|
|
LOCAL_APIC(LU_INT_CMD_LOW) = ipiVector;
|
|
}
|
|
}
|
|
|
|
return TRUE;
|
|
}
|
|
|