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189 lines
3.6 KiB
189 lines
3.6 KiB
/*++
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#include "intelcopy.h"
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Module Name:
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mimisc.c
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Abstract:
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This module contains miscellaneous IA64 specific memory management routines.
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Author:
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ky 28-Jun-96
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Revision History:
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--*/
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#include "mi.h"
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#if 0
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//
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// memory types
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//
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typedef enum _MEM_TYPES {
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RegularMemory,
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MemoryMappedIo,
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VideoDisplayBuffer,
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IoPort,
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RomMemory
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} MEM_TYPES;
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typedef struct _CACHE_ATTRIBUTE_DESCRIPTOR {
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LIST_ENTRY ListEntry;
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MEM_TYPES MemTypes;
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ULONG CacheAttribute;
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PFN_NUMBER BasePage;
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PFN_NUMBER PageCount;
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} CACHE_ATTRIBUTE_DESCRIPTOR, *PCACHE_ATTRIBUTE_DESCRIPTOR;
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LIST_ENTRY MmCacheAttributeDescriptorListHead;
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//
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// default memory cache attributes set in the PTE.
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//
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ULONG MmDefaultCacheAttribute = MM_PTE_MA_WBU; // cacheable, write-back, unordered
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ULONG
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MiCheckMemoryAttribute (
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IN PFN_NUMBER PageFrameNumber
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)
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/*++
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Routine Descrition:
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This function examines the physical address which is given
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by the physical page frame number, and returns the cache
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attributes type for that page. The returned value is used to specify
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the MemoryAttribute field in the HARDWARE_PTE structure to map
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that page.
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This function searches the cache descriptor attribute link
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lists to see if the specific cache attribute is defined for
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that physical address range.
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If the physical address range is not defined in the cache
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descriptor attribute link lists, the default memory attribute is returned.
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Arguments:
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PageFrameIndex - Supplies the physical page frame number to be
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examined for the cache attribute.
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Return Value:
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Returns a cache attribute type for the supplied physical page
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frame number.
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Environment:
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Kernel Mode Only.
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--*/
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{
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PLIST_ENTRY NextMd;
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NextMd = MmCacheAttributeDescriptorListHead.Flink;
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While (NextMd != MmCacheAttributeDescriptorListHead) {
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CacheAttributeDescriptor = CONTAINING_RECORD(NextMd,
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CACHE_ATTRIBUTE_DESCRIPTOR,
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ListEntry);
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if ((PageFrameNumber >= CacheAttributeDescriptor.BasePage) &&
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(PageFrameNumber < CacheAttributeDescriptor.BasePage + CacheAttributeDescriptor.PageCount)) {
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return CacheAttributeDescriptor.CacheAttribute;
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}
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NextMd = CacheAttributeDescriptor->ListEntry.Flink;
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}
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//
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// If the cache memory descriptor is not found,
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// return the default cache attribute, MmDefaultCacheAttribute.
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//
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return MmDefaultCacheAttribute;
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}
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//
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// MmDisableCache yields 0 if cachable, 1 if uncachable.
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//
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UCHAR MmDisableCache[16] = {0, 0, 0, 0, 0, 0, 0, 0
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1, 1, 0, 1, 0, 1, 0, 0};
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MiDisableCaching (
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IN PMMPTE PointerPte
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)
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/*++
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Routine Description:
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This macro takes a valid PTE and sets the caching state to be
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disabled.
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Arguments
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PTE - Supplies a pointer to the valid PTE.
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Return Value:
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None.
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Environment:
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Kernel mode
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--*/
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{
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ULONG CacheAttribute;
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CacheAttribute = MiCheckMemoryAttribute(TempPte.u.Hard.PageFrameNumber);
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if (MmDisableCache[CacheAttribute]) {
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//
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// The returned CacheAttributes indicate uncachable.
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//
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PointerPte->u.Hard.MemAttribute = CacheAttribute;
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} else {
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//
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// Set the most conservative cache memory attribute,
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// UCO (Uncachable, Non-coalescing, Sequential & Non-
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// speculative and Ordered.
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//
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PointerPte->u.Hard.MemAttribute = MM_PTE_MA_UCO;
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}
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}
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#endif
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