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79 lines
5.6 KiB
79 lines
5.6 KiB
// first all the gprs
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{ szGpr0, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR0},
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{ szGpr1, rtCPU | rtRegular | rtExtended | rtInteger | rtFrame, 32, CV_PPC_GPR1},
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{ szGpr2, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR2},
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{ szGpr3, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR3},
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{ szGpr4, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR4},
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{ szGpr5, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR5},
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{ szGpr6, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR6},
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{ szGpr7, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR7},
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{ szGpr8, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR8},
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{ szGpr9, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR9},
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{ szGpr10, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR10},
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{ szGpr11, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR11},
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{ szGpr12, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR12},
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{ szGpr13, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR13},
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{ szGpr14, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR14},
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{ szGpr15, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR15},
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{ szGpr16, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR16},
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{ szGpr17, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR17},
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{ szGpr18, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR18},
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{ szGpr19, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR19},
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{ szGpr20, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR20},
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{ szGpr21, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR21},
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{ szGpr22, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR22},
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{ szGpr23, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR23},
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{ szGpr24, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR24},
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{ szGpr25, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR25},
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{ szGpr26, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR26},
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{ szGpr27, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR27},
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{ szGpr28, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR28},
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{ szGpr29, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR29},
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{ szGpr30, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR30},
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{ szGpr31, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_GPR31},
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// floating point registers follow
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{ szFpr0, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR0 },
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{ szFpr1, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR1 },
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{ szFpr2, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR2 },
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{ szFpr3, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR3 },
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{ szFpr4, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR4 },
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{ szFpr5, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR5 },
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{ szFpr6, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR6 },
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{ szFpr7, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR7 },
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{ szFpr8, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR8 },
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{ szFpr9, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR9 },
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{ szFpr10, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR10 },
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{ szFpr11, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR11 },
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{ szFpr12, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR12 },
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{ szFpr13, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR13 },
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{ szFpr14, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR14 },
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{ szFpr15, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR15 },
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{ szFpr16, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR16 },
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{ szFpr17, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR17 },
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{ szFpr18, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR18 },
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{ szFpr19, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR19 },
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{ szFpr20, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR20 },
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{ szFpr21, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR21 },
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{ szFpr22, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR22 },
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{ szFpr23, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR23 },
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{ szFpr24, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR24 },
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{ szFpr25, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR25 },
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{ szFpr26, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR26 },
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{ szFpr27, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR27 },
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{ szFpr28, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR28 },
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{ szFpr29, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR29 },
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{ szFpr30, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR30 },
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{ szFpr31, rtFPU | rtRegular | rtExtended | rtFloat, 64, CV_PPC_FPR31 },
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{ szFpscr, rtFPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_FPSCR },
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{ szLr, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_LR },
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{ szCr, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_CR },
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{ szCtr, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_PPC_CTR },
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{ szCIA, rtCPU | rtRegular | rtExtended | rtInteger | rtPC, 32, CV_PPC_PC},
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{ szMsr, rtCPU | rtExtended | rtInteger | rtSpecial , 32, CV_PPC_MSR},
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{ szXer, rtCPU | rtExtended | rtInteger | rtSpecial , 32, CV_PPC_XER}
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