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315 lines
8.0 KiB
315 lines
8.0 KiB
/*++
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Copyright (c) 1992 Microsoft Corporation
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Module Name:
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elnkhw.h
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Abstract:
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Hardware specific values for the 3Com Etherlink/MC and Etherlink 16
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NDIS 3.0 driver.
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Author:
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Johnson R. Apacible (JohnsonA) 9-June-1991
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Environment:
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This driver is expected to work in DOS and NT at the equivalent
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of kernel mode.
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Architecturally, there is an assumption in this driver that we are
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on a little endian machine.
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Notes:
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optional-notes
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Revision History:
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--*/
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#ifndef _ELNKHARDWARE_
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#define _ELNKHARDWARE_
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#include <switch.h>
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#define MINIMUM_ETHERNET_PACKET_SIZE ((UINT)60) //64 if FCS included
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#define MAXIMUM_ETHERNET_PACKET_SIZE ((UINT)1514)
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#define ELNK_OFFSET_TO_NEXT_BUFFER ((UINT)1520)
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#define MAXIMUM_CARD_ADDRESS 0xffffff
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#if ELNKMC
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#define ELNKMC_ADAPTER_ID 0x6042
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//
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// Elnkmc defaults
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//
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#define ELNKMC_NUMBER_OF_RECEIVE_BUFFERS ((UINT)8)
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#define ELNKMC_NUMBER_OF_TRANSMIT_BUFFERS ((UINT)2)
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#define ELNKMC_MULTICAST_BLOCK_INDEX ELNKMC_NUMBER_OF_TRANSMIT_BUFFERS
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#else
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//
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// Elnk16 Defaults
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//
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#define ELNK16_DEFAULT_IOBASE 0x300
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#define ELNK16_DEFAULT_INTERRUPT_VECTOR 5
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#define ELNK16_DEFAULT_WINBASE 0xD0000
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#define ELNK16_DEFAULT_WINDOW_SIZE 0x8000
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//
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// Number of receive and transmit buffers for the different Etherlink 16
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// configurations
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//
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#define ELNK16_16K_TRANSMITS ((UINT)2)
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#define ELNK16_16K_RECEIVES ((UINT)8)
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#define ELNK16_32K_TRANSMITS ((UINT)5)
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#define ELNK16_32K_RECEIVES ((UINT)16)
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#define ELNK16_48K_TRANSMITS ((UINT)7)
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#define ELNK16_48K_RECEIVES ((UINT)24)
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#define ELNK16_64K_TRANSMITS ((UINT)10)
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#define ELNK16_64K_RECEIVES ((UINT)32)
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#endif
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//
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// Common Card Registers, these are offsets from Adapter->IoBase
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//
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#define ELNK_STATION_ID 0x00
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#define ELNK_CSR 0x06
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#if ELNKMC
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//
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// Elnkmc Card Register
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//
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#define ELNKMC_REVISION_LEVEL 0x07
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#else
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//
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// Elnk16 Card Registers, these are offsets from Adapter->IoBase
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//
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#define ELNK16_3COM 0x00
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#define ELNK16_INTCLR 0x0A
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#define ELNK16_CAR 0x0B
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#define ELNK16_ROM_CONFIG 0x0D
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#define ELNK16_RAM_CONFIG 0x0E
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#define ELNK16_ICR 0x0F
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//
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// Etherlink 16 ID Port
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//
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#define ELNK16_ID_PORT 0x100
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#endif // ELNKMC
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//
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// CSR bits
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//
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#define CSR_BANK_SELECT_MASK 0x03
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#define CSR_INTEN 0x04
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#define CSR_INT_ACTIVE 0x08
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#define CSR_LOOP_BACK_ENABLE 0x20
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#define CSR_CA 0x40
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#define CSR_RESET 0x80
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//
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// ROMCR bits
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//
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#define ROMCR_BNC 0x80
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#if ELNKMC
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//
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// Elnkmc CSR Values
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//
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#define CSR_DEFAULT CSR_BANK_SELECT_MASK |\
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CSR_INTEN |\
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CSR_RESET
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#else
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//
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// Elnk16 CSR Values
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//
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#define CSR_DEFAULT CSR_INTEN |\
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CSR_RESET
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//
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// Elnk16 ICR Values
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//
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#define ICR_RESET 0x10
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#endif
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//
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// Our buffer sizes.
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//
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// These are *not* configurable. Portions of the code assumes
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// that these buffers can contain *any* legal Ethernet packet.
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//
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#define ELNK_SIZE_OF_RECEIVE_BUFFERS (MAXIMUM_ETHERNET_PACKET_SIZE)
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//
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// Miscellaneous Constants
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//
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#define ELNK_NULL ((USHORT)0xffff)
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#define ELNK_EMPTY ((UINT)0xffff)
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#define ELNK_IMMEDIATE_DATA_LENGTH ((UINT)64)
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#define ELNK_MAXIMUM_MULTICAST 16
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//
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// Miscellaneous macros
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//
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#define WRITE_ADAPTER_REGISTER(_Adapter, _Offset, _Value) \
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NdisWriteRegisterUshort((PUSHORT)((_Adapter)->SharedRam + \
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(_Offset) - (_Adapter)->CardOffset), (_Value))
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#define READ_ADAPTER_REGISTER(_Adapter, _Offset, _pValue) \
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NdisReadRegisterUshort((PUSHORT) ((_Adapter)->SharedRam + \
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(_Offset) - (_Adapter->CardOffset)), (_pValue))
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//
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// read and writes from ports
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//
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#define ELNK_READ_UCHAR(_Adapter, _Offset, _pValue) \
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NdisReadPortUchar( \
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(_Adapter)->NdisAdapterHandle,\
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(ULONG)((_Adapter)->IoBase+(_Offset)), \
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(PUCHAR)(_pValue) \
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)
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#define ELNK_WRITE_UCHAR(_Adapter, _Offset, _Value) \
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NdisWritePortUchar( \
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(_Adapter)->NdisAdapterHandle, \
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(ULONG)((_Adapter)->IoBase+(_Offset)), \
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(UCHAR) (_Value) \
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)
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#if ELNKMC
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#define ELNKMC_READ_POS(_Offset) \
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READ_PORT_UCHAR( \
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(PUCHAR)(_Offset) \
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)
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#define ELNKMC_WRITE_POS(_Offset, _Value) \
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WRITE_PORT_UCHAR( \
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(PUCHAR) (_Offset), \
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(UCHAR) (_Value) \
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)
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#endif
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#define ELNK_DISABLE_INTERRUPT { \
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Adapter->CurrentCsr &= ~CSR_INTEN; \
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ELNK_WRITE_UCHAR(Adapter, ELNK_CSR, Adapter->CurrentCsr); \
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}
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#define ELNK_ENABLE_INTERRUPT { \
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Adapter->CurrentCsr |= CSR_INTEN; \
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ELNK_WRITE_UCHAR(Adapter, ELNK_CSR, Adapter->CurrentCsr); \
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}
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//
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// This pauses execution until a pending command to the adapter
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// has been accepted by the 586
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//
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#define ELNK_WAIT { \
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UINT _i; \
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USHORT _ScbCmd; \
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for (_i = 0; _i <= 20000 ; _i++ ) { \
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READ_ADAPTER_REGISTER(Adapter, OFFSET_SCBCMD, &_ScbCmd);\
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if (_ScbCmd == 0) { \
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break; \
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} \
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NdisStallExecution(50); \
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} \
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}
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#if ELNKMC
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//
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// This is the Etherlink/MC Channel Attention macro and is how we
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// interrupt the card. We need a 500ns delay between the 2 writes.
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//
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#define ELNK_CA { \
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ELNK_WRITE_UCHAR(Adapter, ELNK_CSR, Adapter->CurrentCsr | CSR_CA); \
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NdisStallExecution(1); \
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ELNK_WRITE_UCHAR(Adapter, ELNK_CSR, Adapter->CurrentCsr); \
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}
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#else
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//
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// This is the Channel Attention macro and is how we interrupt the card.
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//
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#define ELNK_CA ELNK_WRITE_UCHAR(Adapter, ELNK16_CAR, 0x00)
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#endif
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//
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// Get the card address given the host address
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//
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#define ELNK_GET_CARD_ADDRESS(_Adapter, _Virtual) (USHORT) \
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((ULONG)(_Virtual) - (ULONG)((_Adapter)->SharedRam) + (_Adapter)->CardOffset)
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//
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// Get the host offset given card address
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//
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#define ELNK_GET_HOST_ADDRESS(_Adapter, _CardAddress) ((PUCHAR) \
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((_Adapter)->SharedRam) + (_CardAddress) - (_Adapter)->CardOffset)
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#include <82586.h>
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//
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// MCA stuff for the Etherlink/MC card
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//
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#if ELNKMC
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//
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// Use this register to select which channel (slot) is being configured
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//
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#define POS_CHANNEL_SELECT 0x96
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//
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// or this with the channel number to select new channel
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//
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#define POS_NEW_CHANNEL_CODE 0x08
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//
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// each card has an ID that can be used to identify it
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//
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#define POS_CARD_ID_1 0x100
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#define POS_CARD_ID_2 0x101
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//
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// Etherlink MCA card ID
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//
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#define ELNKMC_CARD_ID_1 ((UCHAR)0x42)
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#define ELNKMC_CARD_ID_2 ((UCHAR)0x60)
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//
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// Card specific registers
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//
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#define POS_CARD_REGISTER_1 0x102
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#define POS_CARD_REGISTER_2 0x103
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//
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// register one bits
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//
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#define REG1_CARD_ENABLE 0x01
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#define REG1_IO_BASE_MASK 0x06
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#define REG1_RAM_BASE_MASK 0x18
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#define REG1_ON_BOARD_TRANSCEIVER 0x20
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#define REG1_INTERRUPT_LEVEL_MASK 0xC0
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//
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// register 2 (used for setting system interrupt level)
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//
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#define REG2_INTERRUPT_LEVEL_MASK 0x0F
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//
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// Misc defines
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//
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#define MCA_MAX_NUMBER_OF_CHANNELS 0x08
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#endif
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#endif // _ELNKHARDWARE_
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