Leaked source code of windows server 2003
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  1. //***************************************************************************
  2. //
  3. // Module Name:
  4. //
  5. // TVP4020.h
  6. //
  7. // Abstract:
  8. //
  9. // This module contains the definitions for the P2 internal RAMDAC.
  10. //
  11. // Environment:
  12. //
  13. // Kernel mode
  14. //
  15. //
  16. // Copyright (c) 1995 AccelGraphics, Inc.
  17. //
  18. //***************************************************************************
  19. //
  20. // TI TVP4020 RAMDAC definitions
  21. // This set of registers resides at &(pCtrlRegs->ExternalVideo)
  22. //
  23. typedef struct _tvp4020_regs {
  24. RAMDAC_REG pciAddrWr; // 0x00 - palette/cursor RAM write address, Index Register
  25. RAMDAC_REG palData; // 0x01 - palette RAM data
  26. RAMDAC_REG pixelMask; // 0x02 - pixel read mask
  27. RAMDAC_REG pciAddrRd; // 0x03 - palette/cursor RAM read address
  28. RAMDAC_REG curColAddr; // 0x04 - cursor color address
  29. RAMDAC_REG curColData; // 0x05 - cursor color data
  30. RAMDAC_REG Reserved1; // 0x06 - reserved
  31. RAMDAC_REG Reserved2; // 0x07 - reserved
  32. RAMDAC_REG Reserved3; // 0x08 - reserved
  33. RAMDAC_REG Reserved4; // 0x09 - reserved
  34. RAMDAC_REG indexData; // 0x0A - indexed data
  35. RAMDAC_REG curRAMData; // 0x0B - cursor RAM data
  36. RAMDAC_REG cursorXLow; // 0x0C - cursor position X low byte
  37. RAMDAC_REG cursorXHigh; // 0x0D - cursor position X high byte
  38. RAMDAC_REG cursorYLow; // 0x0E - cursor position Y low byte
  39. RAMDAC_REG cursorYHigh; // 0x0F - cursor position Y high byte
  40. } TVP4020RAMDAC, *pTVP4020RAMDAC;
  41. //
  42. // macro declared by any function wishing to use the P2 internal RAMDAC . MUST be declared
  43. // after P2_DECL.
  44. //
  45. #define TVP4020_DECL \
  46. pTVP4020RAMDAC pTVP4020Regs = (pTVP4020RAMDAC)(hwDeviceExtension->pRamdac)
  47. //
  48. // use the following macros as the address to pass to the
  49. // VideoPortWriteRegisterUlong function
  50. //
  51. // Palette Access
  52. #define __TVP4020_PAL_WR_ADDR ((PULONG)&(pTVP4020Regs->pciAddrWr.reg))
  53. #define __TVP4020_PAL_RD_ADDR ((PULONG)&(pTVP4020Regs->pciAddrRd.reg))
  54. #define __TVP4020_PAL_DATA ((PULONG)&(pTVP4020Regs->palData.reg))
  55. //
  56. // Pixel mask
  57. //
  58. #define __TVP4020_PIXEL_MASK ((PULONG)&(pTVP4020Regs->pixelMask.reg))
  59. //
  60. // Access to the indexed registers
  61. //
  62. #define __TVP4020_INDEX_ADDR ((PULONG)&(pTVP4020Regs->pciAddrWr.reg))
  63. #define __TVP4020_INDEX_DATA ((PULONG)&(pTVP4020Regs->indexData.reg))
  64. //
  65. // Access to the Cursor
  66. //
  67. #define __TVP4020_CUR_RAM_WR_ADDR ((PULONG)&(pTVP4020Regs->pciAddrWr.reg))
  68. #define __TVP4020_CUR_RAM_RD_ADDR ((PULONG)&(pTVP4020Regs->palAddrRd.reg))
  69. #define __TVP4020_CUR_RAM_DATA ((PULONG)&(pTVP4020Regs->curRAMData.reg))
  70. #define __TVP4020_CUR_COL_ADDR ((PULONG)&(pTVP4020Regs->curColAddr.reg))
  71. #define __TVP4020_CUR_COL_DATA ((PULONG)&(pTVP4020Regs->curColData.reg))
  72. //
  73. // Cursor position control
  74. //
  75. #define __TVP4020_CURSOR_X_LSB ((PULONG)&(pTVP4020Regs->cursorXLow.reg))
  76. #define __TVP4020_CURSOR_X_MSB ((PULONG)&(pTVP4020Regs->cursorXHigh.reg))
  77. #define __TVP4020_CURSOR_Y_LSB ((PULONG)&(pTVP4020Regs->cursorYLow.reg))
  78. #define __TVP4020_CURSOR_Y_MSB ((PULONG)&(pTVP4020Regs->cursorYHigh.reg))
  79. // ----------------------Values for some direct registers-----------------------
  80. /********************************************************************************/
  81. /* DIRECT REGISTER - CURSOR POSITION CONTROL */
  82. /********************************************************************************/
  83. //
  84. // ** TVP4020_CUR_X_LSB
  85. // ** TVP4020_CUR_X_MSB
  86. // ** TVP4020_CUR_Y_LSB
  87. // ** TVP4020_CUR_Y_MSB
  88. // Default - undefined
  89. // Values written into those registers represent the BOTTOM-RIGHT corner
  90. // of the cursor. If 0 is in X or Y position - the cursor is off the screen
  91. // Only 12 bits are used, giving the range from 0 to 4095 ( 0x0000 - 0x0FFF)
  92. // The size of the cursor is (64,64) (0x40, 0x40)
  93. //
  94. #define TVP4020_CURSOR_OFFSCREEN 0x00 // Cursor offscreen
  95. /********************************************************************************/
  96. /* DIRECT REGISTER - CURSOR COLORS */
  97. /********************************************************************************/
  98. #define TVP4020_CURSOR_COLOR0 0x01
  99. #define TVP4020_CURSOR_COLOR1 0x02
  100. #define TVP4020_CURSOR_COLOR2 0x03
  101. /********************************************************************************/
  102. /* INDIRECT REGISTER - CURSOR CONTROL */
  103. /********************************************************************************/
  104. #define __TVP4020_CURSOR_CONTROL 0x06 // Indirect cursor control -
  105. // Default - 0x00
  106. #define TVP4020_CURSOR_SIZE_32 (0 << 6)// 32x32 cursor
  107. #define TVP4020_CURSOR_SIZE_64 (1 << 6)// 32x32 cursor
  108. #define TVP4020_CURSOR_32_SEL(i) ((i) << 4)// one of 4 32x32 cursors DABO: changed to << 4
  109. #define TVP4020_CURSOR_RAM_ADDRESS(x) (((x) & 0x03) << 2)// High bits of cursor RAM address
  110. #define TVP4020_CURSOR_RAM_MASK ((0x03) << 2) // Mask for high bits of cursor RAM address
  111. // DABO: Added constants for cursor mode
  112. #define TVP4020_CURSOR_OFF 0x00 // Cursor off
  113. #define TVP4020_CURSOR_COLOR 0x01 // 2-bits select color
  114. #define TVP4020_CURSOR_XGA 0x02 // 2-bits select XOR
  115. #define TVP4020_CURSOR_XWIN 0x03 // 2-bits select transparency/color
  116. /********************************************************************************/
  117. /* INDIRECT REGISTER - COLOR MODE REGISTER */
  118. /********************************************************************************/
  119. #define __TVP4020_COLOR_MODE 0x18 // Color Mode Register
  120. // Default - 0x00
  121. #define TVP4020_TRUE_COLOR_ENABLE (1 << 7)// True Color data accesses LUT
  122. #define TVP4020_TRUE_COLOR_DISABLE (0 << 7)// Non true color accesses LUT
  123. #define TVP4020_RGB_MODE (1 << 5)// RGB mode DABO: Swapped 0/1 (0=BGR, 1=RGB)
  124. #define TVP4020_BGR_MODE (0 << 5)// BGR mode
  125. #define TVP4020_VGA_SELECT (0 << 4)// select VGA mode
  126. #define TVP4020_GRAPHICS_SELECT (1 << 4)// select graphics modes
  127. #define TVP4020_PIXEL_MODE_CI8 (0 << 0)// pseudo color or VGA mode
  128. #define TVP4020_PIXEL_MODE_332 (1 << 0)// 332 true color
  129. #define TVP4020_PIXEL_MODE_2320 (2 << 0)// 232 off
  130. #define TVP4020_PIXEL_MODE_2321 (3 << 0)//
  131. #define TVP4020_PIXEL_MODE_5551 (4 << 0)//
  132. #define TVP4020_PIXEL_MODE_4444 (5 << 0)//
  133. #define TVP4020_PIXEL_MODE_565 (6 << 0)//
  134. #define TVP4020_PIXEL_MODE_8888 (8 << 0)//
  135. #define TVP4020_PIXEL_MODE_PACKED (9 << 0)// 24 bit packed
  136. /********************************************************************************/
  137. /* INDIRECT REGISTER - MODE CONTROL REGISTER */
  138. /********************************************************************************/
  139. #define __TVP4020_MODE_CONTROL 0x19 // Mode control
  140. // Default - 0x00
  141. #define TVP4020_PRIMARY_INPUT (0 << 4)// Primary input throuh palette
  142. #define TVP4020_SECONDARY_INPUT (1 << 4)// Secondary input throuh palette
  143. #define TVP4020_5551_DBL_BUFFER (1 << 2)// Enable 5551 dbl buffer
  144. #define TVP4020_5551_PACKED (0 << 2)// Packed 555 mode
  145. #define TVP4020_ENABLE_STATIC_DBL_BUFFER (1 << 1)// Static dbl buffer enabled
  146. #define TVP4020_DISABLE_STATIC_DBL_BUFFER (1 << 1)// Static dbl buffer disabled
  147. #define TVP4020_SELECT_FRONT_MODE (0 << 0)// Front mode
  148. #define TVP4020_SELECT_BACK_MODE (1 << 0)// Back mode
  149. /********************************************************************************/
  150. /* INDIRECT REGISTER - PALETTE PAGE */
  151. /********************************************************************************/
  152. #define __TVP4020_PALETTE_PAGE 0x1C //
  153. // Default - 0x00
  154. /********************************************************************************/
  155. /* INDIRECT REGISTER - MISC CONTROL */
  156. /********************************************************************************/
  157. #define __TVP4020_MISC_CONTROL 0x1E //
  158. // Default - 0x00
  159. #define TVP4020_SYNC_ENABLE (1 << 5)// Output SYNC info onto IOG
  160. #define TVP4020_SYNC_DISABLE (0 << 5)// No SYNC IOG output
  161. #define TVP4020_PEDESTAL_0 (0 << 4)// 0 IRE blanking pedestal
  162. #define TVP4020_PEDESTAL_75 (1 << 4)// 7.5 IRE blanking pedestal
  163. #define TVP4020_VSYNC_INVERT (1 << 3)// invert VSYNC output polarity
  164. #define TVP4020_VSYNC_NORMAL (0 << 3)// normal VSYNC output polarity
  165. #define TVP4020_HSYNC_INVERT (1 << 2)// invert HSYNC output polarity
  166. #define TVP4020_HSYNC_NORMAL (0 << 3)// normal HSYNC output polarity
  167. #define TVP4020_DAC_8BIT (1 << 1)// DAC is in 8-bit mode
  168. #define TVP4020_DAC_6BIT (0 << 1)// DAC is in 6-bit mode
  169. #define TVP4020_DAC_POWER_ON (0 << 0)// Turn DAC Power on
  170. #define TVP4020_DAC_POWER_OFF (1 << 0)// Turn DAC Power off
  171. /********************************************************************************/
  172. /* INDIRECT REGISTER - COLOR KEY CONTROL */
  173. /********************************************************************************/
  174. #define __TVP4020_CK_CONTROL 0x40 //
  175. // Default - 0x00
  176. /********************************************************************************/
  177. /* INDIRECT REGISTER - COLOR KEY OVERLAY */
  178. /********************************************************************************/
  179. #define __TVP4020_CK_OVR_REG 0x41 //
  180. // Default - 0x00
  181. /********************************************************************************/
  182. /* INDIRECT REGISTER - COLOR KEY RED */
  183. /********************************************************************************/
  184. #define __TVP4020_CK_RED_REG 0x42 //
  185. // Default - 0x00
  186. /********************************************************************************/
  187. /* INDIRECT REGISTER - COLOR KEY GREEN */
  188. /********************************************************************************/
  189. #define __TVP4020_CK_GREEN_REG 0x43 //
  190. // Default - 0x00
  191. /********************************************************************************/
  192. /* INDIRECT REGISTER - COLOR KEY BLUE */
  193. /********************************************************************************/
  194. #define __TVP4020_CK_BLUE_REG 0x44 //
  195. // Default - 0x00
  196. /********************************************************************************/
  197. /* INDIRECT REGISTER - PIXEL CLOCK PLL */
  198. /********************************************************************************/
  199. #define __TVP4020_PIXCLK_REG_A1 0x20
  200. #define __TVP4020_PIXCLK_REG_A2 0x21
  201. #define __TVP4020_PIXCLK_REG_A3 0x22
  202. #define __TVP4020_PIXCLK_REG_B1 0x23
  203. #define __TVP4020_PIXCLK_REG_B2 0x24
  204. #define __TVP4020_PIXCLK_REG_B3 0x25
  205. #define __TVP4020_PIXCLK_REG_C1 0x26
  206. #define __TVP4020_PIXCLK_REG_C2 0x27
  207. #define __TVP4020_PIXCLK_REG_C3 0x28
  208. #define __TVP4020_PIXCLK_STATUS 0x29
  209. /********************************************************************************/
  210. /* INDIRECT REGISTER - MEMORU CLOCK PLL */
  211. /********************************************************************************/
  212. #define __TVP4020_MEMCLK_REG_1 0x30
  213. #define __TVP4020_MEMCLK_REG_2 0x31
  214. #define __TVP4020_MEMCLK_REG_3 0x32
  215. #define __TVP4020_MEMCLK_STATUS 0x33
  216. #if 0
  217. // need a delay between each write to the 4020. The only way to guarantee
  218. // that the write has completed is to read from a Permedia2 control register.
  219. // Reading forces any posted writes to be flushed out.
  220. #define TVP4020_DELAY \
  221. { \
  222. volatile LONG __junk; \
  223. __junk = VideoPortReadRegisterUlong (FB_MODE_SEL); \
  224. __junk = VideoPortReadRegisterUlong (FB_MODE_SEL); \
  225. }
  226. #else
  227. #define TVP4020_DELAY
  228. #endif
  229. // macro to load a given data value into an internal TVP4020 register.
  230. //
  231. #define TVP4020_SET_INDEX_REG(index) \
  232. { \
  233. DEBUG_PRINT((3, "*(0x%X) <-- 0x%X\n", __TVP4020_INDEX_ADDR, (index) & 0xff)); \
  234. VideoPortWriteRegisterUlong(__TVP4020_INDEX_ADDR, (ULONG)((index) & 0xff)); \
  235. TVP4020_DELAY; \
  236. }
  237. #define TVP4020_WRITE_INDEX_REG(index, data) \
  238. { \
  239. TVP4020_SET_INDEX_REG(index); \
  240. DEBUG_PRINT((3, "*(0x%X) <-- 0x%X\n", __TVP4020_INDEX_DATA, (data) & 0xff)); \
  241. VideoPortWriteRegisterUlong(__TVP4020_INDEX_DATA, (ULONG)((data) & 0xff)); \
  242. TVP4020_DELAY; \
  243. }
  244. #define TVP4020_READ_INDEX_REG(index, data) \
  245. { \
  246. TVP4020_SET_INDEX_REG(index); \
  247. data = VideoPortReadRegisterUlong(__TVP4020_INDEX_DATA) & 0xff; \
  248. TVP4020_DELAY; \
  249. DEBUG_PRINT((3, "0x%X <-- *(0x%X)\n", data, __TVP4020_INDEX_DATA)); \
  250. }
  251. // DABO: For compatibility with TVP3026
  252. #define TVP4020_LOAD_CURSOR_CTRL(data) \
  253. { \
  254. volatile LONG __temp; \
  255. TVP4020_READ_INDEX_REG(__TVP4020_CURSOR_CONTROL, __temp); \
  256. __temp &= ~(0x03) ; \
  257. __temp |= ((data) & 0x03) ; \
  258. TVP4020_WRITE_INDEX_REG(__TVP4020_CURSOR_CONTROL, __temp); \
  259. }
  260. //
  261. // macros to write a given RGB triplet into cursors 0, 1 and 2
  262. //
  263. #define TVP4020_SET_CURSOR_COLOR0(red, green, blue) \
  264. { \
  265. VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_ADDR, (ULONG)(TVP4020_CURSOR_COLOR0)); \
  266. TVP4020_DELAY; \
  267. VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_DATA, (ULONG)(red)); \
  268. TVP4020_DELAY; \
  269. VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_DATA, (ULONG)(green)); \
  270. TVP4020_DELAY; \
  271. VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_DATA, (ULONG)(blue)); \
  272. TVP4020_DELAY; \
  273. }
  274. #define TVP4020_SET_CURSOR_COLOR1(red, green, blue) \
  275. { \
  276. VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_ADDR, (ULONG)(TVP4020_CURSOR_COLOR1)); \
  277. TVP4020_DELAY; \
  278. VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_DATA, (ULONG)(red)); \
  279. TVP4020_DELAY; \
  280. VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_DATA, (ULONG)(green)); \
  281. TVP4020_DELAY; \
  282. VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_DATA, (ULONG)(blue)); \
  283. TVP4020_DELAY; \
  284. }
  285. #define TVP4020_SET_CURSOR_COLOR2(red, green, blue) \
  286. { \
  287. VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_ADDR, (ULONG)(TVP4020_CURSOR_COLOR2)); \
  288. TVP4020_DELAY; \
  289. VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_DATA, (ULONG)(red)); \
  290. TVP4020_DELAY; \
  291. VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_DATA, (ULONG)(green)); \
  292. TVP4020_DELAY; \
  293. VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_DATA, (ULONG)(blue)); \
  294. TVP4020_DELAY; \
  295. }
  296. //
  297. // macros to load a given RGB triple into the TVP4020 palette. Send the starting
  298. // index and then send RGB triples. Auto-increment is turned on.
  299. // Use TVP4020_PALETTE_START and multiple TVP4020_LOAD_PALETTE calls to load
  300. // a contiguous set of entries. Use TVP4020_LOAD_PALETTE_INDEX to load a set
  301. // of sparse entries.
  302. //
  303. #define TVP4020_PALETTE_START_WR(index) \
  304. { \
  305. VideoPortWriteRegisterUlong(__TVP4020_PAL_WR_ADDR, (ULONG)(index)); \
  306. TVP4020_DELAY; \
  307. }
  308. #define TVP4020_PALETTE_START_RD(index) \
  309. { \
  310. VideoPortWriteRegisterUlong(__TVP4020_PAL_RD_ADDR, (ULONG)(index)); \
  311. TVP4020_DELAY; \
  312. }
  313. #define TVP4020_LOAD_PALETTE(red, green, blue) \
  314. { \
  315. VideoPortWriteRegisterUlong(__TVP4020_PAL_DATA, (ULONG)(red)); \
  316. TVP4020_DELAY; \
  317. VideoPortWriteRegisterUlong(__TVP4020_PAL_DATA, (ULONG)(green)); \
  318. TVP4020_DELAY; \
  319. VideoPortWriteRegisterUlong(__TVP4020_PAL_DATA, (ULONG)(blue)); \
  320. TVP4020_DELAY; \
  321. }
  322. #define TVP4020_LOAD_PALETTE_INDEX(index, red, green, blue) \
  323. { \
  324. VideoPortWriteRegisterUlong(__TVP4020_PAL_WR_ADDR, (ULONG)(index)); \
  325. TVP4020_DELAY; \
  326. VideoPortWriteRegisterUlong(__TVP4020_PAL_DATA, (ULONG)(red)); \
  327. TVP4020_DELAY; \
  328. VideoPortWriteRegisterUlong(__TVP4020_PAL_DATA, (ULONG)(green)); \
  329. TVP4020_DELAY; \
  330. VideoPortWriteRegisterUlong(__TVP4020_PAL_DATA, (ULONG)(blue)); \
  331. TVP4020_DELAY; \
  332. }
  333. //
  334. // macro to read back a given RGB triple from the TVP4020 palette. Use after
  335. // a call to TVP4020_PALETTE_START_RD
  336. //
  337. #define TVP4020_READ_PALETTE(red, green, blue) \
  338. { \
  339. red = (UCHAR)(VideoPortReadRegisterUlong(__TVP4020_PAL_DATA) & 0xff); \
  340. TVP4020_DELAY; \
  341. green = (UCHAR)(VideoPortReadRegisterUlong(__TVP4020_PAL_DATA) & 0xff); \
  342. TVP4020_DELAY; \
  343. blue = (UCHAR)(VideoPortReadRegisterUlong(__TVP4020_PAL_DATA) & 0xff); \
  344. TVP4020_DELAY; \
  345. }
  346. //
  347. // macros to set/get the pixel read mask. The mask is 8 bits wide and gets
  348. // replicated across all bytes that make up a pixel.
  349. //
  350. #define TVP4020_SET_PIXEL_READMASK(mask) \
  351. { \
  352. VideoPortWriteRegisterUlong(__TVP4020_PIXEL_MASK, (ULONG)(mask)); \
  353. TVP4020_DELAY; \
  354. }
  355. #define TVP4020_READ_PIXEL_READMASK(mask) \
  356. { \
  357. mask = VideoPortReadRegisterUlong(__TVP4020_PIXEL_MASK) & 0xff; \
  358. }
  359. //
  360. // macros to load values into the cursor array
  361. //
  362. #define TVP4020_CURSOR_ARRAY_START(offset) \
  363. { \
  364. volatile LONG __temp; \
  365. TVP4020_READ_INDEX_REG(__TVP4020_CURSOR_CONTROL, __temp); \
  366. __temp &= ~TVP4020_CURSOR_RAM_MASK ; \
  367. __temp |= TVP4020_CURSOR_RAM_ADDRESS((offset)>> 8) ; \
  368. TVP4020_WRITE_INDEX_REG(__TVP4020_CURSOR_CONTROL, __temp); \
  369. VideoPortWriteRegisterUlong(__TVP4020_CUR_RAM_WR_ADDR, (ULONG)((offset)& 0xff)); \
  370. TVP4020_DELAY; \
  371. }
  372. //
  373. // DABO: Need a similar macro to set the read address for cursor RAM?
  374. // DABO: changed to __TVP4020_CUR_RAM_DATA
  375. //
  376. #define TVP4020_LOAD_CURSOR_ARRAY(data) \
  377. { \
  378. VideoPortWriteRegisterUlong(__TVP4020_CUR_RAM_DATA, (ULONG)(data)); \
  379. TVP4020_DELAY; \
  380. }
  381. //
  382. // DABO: changed to __TVP4020_CUR_RAM_DATA
  383. //
  384. #define TVP4020_READ_CURSOR_ARRAY(data) \
  385. { \
  386. data = VideoPortReadRegisterUlong(__TVP4020_CUR_RAM_DATA) & 0xff; \
  387. TVP4020_DELAY; \
  388. }
  389. //
  390. // macro to move the cursor
  391. //
  392. #define TVP4020_MOVE_CURSOR(x, y) \
  393. { \
  394. VideoPortWriteRegisterUlong(__TVP4020_CURSOR_X_LSB, (ULONG)((x) & 0xff)); \
  395. TVP4020_DELAY; \
  396. VideoPortWriteRegisterUlong(__TVP4020_CURSOR_X_MSB, (ULONG)((x) >> 8)); \
  397. TVP4020_DELAY; \
  398. VideoPortWriteRegisterUlong(__TVP4020_CURSOR_Y_LSB, (ULONG)((y) & 0xff)); \
  399. TVP4020_DELAY; \
  400. VideoPortWriteRegisterUlong(__TVP4020_CURSOR_Y_MSB, (ULONG)((y) >> 8)); \
  401. TVP4020_DELAY; \
  402. }
  403. //
  404. // macro to change the cursor hotspot
  405. //
  406. #define TVP4020_CURSOR_HOTSPOT(x, y) \
  407. { \
  408. TVP4020_DELAY; \
  409. }