Leaked source code of windows server 2003
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  1. //***************************************************************************
  2. //
  3. // Module Name:
  4. //
  5. // p2rd.h
  6. //
  7. // Abstract:
  8. //
  9. // This module contains the definitions for the 3Dlabs P2ST RAMDAC
  10. //
  11. // Environment:
  12. //
  13. // Kernel mode
  14. //
  15. //
  16. // Copyright (c) 1994-1998 3Dlabs Inc. Ltd. All rights reserved.
  17. // Copyright (c) 1995-1999 Microsoft Corporation. All Rights Reserved.
  18. //
  19. //***************************************************************************
  20. //
  21. // structure with all the direct access registers
  22. //
  23. typedef struct _p2rd_regs
  24. {
  25. RAMDAC_REG RDPaletteWriteAddress;
  26. RAMDAC_REG RDPaletteData;
  27. RAMDAC_REG RDPixelMask;
  28. RAMDAC_REG RDPaletteAddressRead;
  29. RAMDAC_REG RDIndexLow;
  30. RAMDAC_REG RDIndexHigh;
  31. RAMDAC_REG RDIndexedData;
  32. RAMDAC_REG RDIndexControl;
  33. }
  34. P2RDRAMDAC;
  35. //
  36. // macro declared by any function wishing to use the RGB525 RAMDAC. MUST be declared
  37. // after P2_DECL.
  38. //
  39. #define P2RD_DECL \
  40. P2RDRAMDAC *pP2RDRegs = (P2RDRAMDAC *)hwDeviceExtension->pRamdac
  41. //
  42. // use the following macros as the address to pass to the
  43. // VideoPortWriteRegisterUlong function
  44. //
  45. #define P2RD_PAL_WR_ADDR ((PULONG)&(pP2RDRegs->RDPaletteWriteAddress.reg))
  46. #define P2RD_PAL_RD_ADDR ((PULONG)&(pP2RDRegs->RDPaletteAddressRead.reg))
  47. #define P2RD_PAL_DATA ((PULONG)&(pP2RDRegs->RDPaletteData.reg))
  48. #define P2RD_PIXEL_MASK ((PULONG)&(pP2RDRegs->RDPixelMask.reg))
  49. #define P2RD_INDEX_ADDR_LO ((PULONG)&(pP2RDRegs->RDIndexLow.reg))
  50. #define P2RD_INDEX_ADDR_HI ((PULONG)&(pP2RDRegs->RDIndexHigh.reg))
  51. #define P2RD_INDEX_DATA ((PULONG)&(pP2RDRegs->RDIndexedData.reg))
  52. #define P2RD_INDEX_CONTROL ((PULONG)&(pP2RDRegs->RDIndexControl.reg))
  53. //
  54. // bit field definitions for the direct access registers
  55. //
  56. #define P2RD_IDX_CTL_AUTOINCREMENT_ENABLED 0x01
  57. //
  58. // indexed register definitions accessed via P2RD_LOAD_INDEX_REG() and P2RD_READ_INDEX_REG()
  59. //
  60. #define P2RD_MISC_CONTROL 0x0000
  61. #define P2RD_SYNC_CONTROL 0x0001
  62. #define P2RD_DAC_CONTROL 0x0002
  63. #define P2RD_PIXEL_SIZE 0x0003
  64. #define P2RD_COLOR_FORMAT 0x0004
  65. #define P2RD_CURSOR_MODE 0x0005
  66. #define P2RD_CURSOR_CONTROL 0x0006
  67. #define P2RD_CURSOR_X_LOW 0x0007
  68. #define P2RD_CURSOR_X_HIGH 0x0008
  69. #define P2RD_CURSOR_Y_LOW 0x0009
  70. #define P2RD_CURSOR_Y_HIGH 0x000a
  71. #define P2RD_CURSOR_HOTSPOT_X 0x000b
  72. #define P2RD_CURSOR_HOTSPOT_Y 0x000c
  73. #define P2RD_OVERLAY_KEY 0x000d
  74. #define P2RD_PAN 0x000e
  75. #define P2RD_SENSE 0x000f
  76. #define P2RD_CHECK_CONTROL 0x0018
  77. #define P2RD_CHECK_PIXEL_RED 0x0019
  78. #define P2RD_CHECK_PIXEL_GREEN 0x001a
  79. #define P2RD_CHECK_PIXEL_BLUE 0x001b
  80. #define P2RD_CHECK_LUT_RED 0x001c
  81. #define P2RD_CHECK_LUT_GREEN 0x001d
  82. #define P2RD_CHECK_LUT_BLUE 0x001e
  83. #define P2RD_DCLK_SETUP_1 0x01f0
  84. #define P2RD_DCLK_SETUP_2 0x01f1
  85. #define P2RD_MCLK_SETUP_1 0x01f2
  86. #define P2RD_MCLK_SETUP_2 0x01f3
  87. #define P2RD_DCLK_CONTROL 0x0200
  88. #define P2RD_DCLK0_PRE_SCALE 0x0201
  89. #define P2RD_DCLK0_FEEDBACK_SCALE 0x0202
  90. #define P2RD_DCLK0_POST_SCALE 0x0203
  91. #define P2RD_DCLK1_PRE_SCALE 0x0204
  92. #define P2RD_DCLK1_FEEDBACK_SCALE 0x0205
  93. #define P2RD_DCLK1_POST_SCALE 0x0206
  94. #define P2RD_DCLK2_PRE_SCALE 0x0207
  95. #define P2RD_DCLK2_FEEDBACK_SCALE 0x0208
  96. #define P2RD_DCLK2_POST_SCALE 0x0209
  97. #define P2RD_DCLK3_PRE_SCALE 0x020a
  98. #define P2RD_DCLK3_FEEDBACK_SCALE 0x020b
  99. #define P2RD_DCLK3_POST_SCALE 0x020c
  100. #define P2RD_MCLK_CONTROL 0x020d
  101. #define P2RD_MCLK_PRE_SCALE 0x020e
  102. #define P2RD_MCLK_FEEDBACK_SCALE 0x020f
  103. #define P2RD_MCLK_POST_SCALE 0x0210
  104. #define P2RD_CURSOR_PALETTE_START 0x0303 // 303..32f
  105. #define P2RD_CURSOR_PATTERN_START 0x0400 // 400..7ff
  106. //
  107. // bit field definitions for the indexed registers
  108. //
  109. #define P2RD_MISC_CONTROL_OVERLAYS_ENABLED 0x10
  110. #define P2RD_MISC_CONTROL_DIRECT_COLOR_ENABLED 0x08
  111. #define P2RD_MISC_CONTROL_PIXEL_DOUBLE 0x02
  112. #define P2RD_MISC_CONTROL_HIGHCOLORRES 0x01
  113. #define P2RD_SYNC_CONTROL_VSYNC_ACTIVE_LOW 0x00
  114. #define P2RD_SYNC_CONTROL_VSYNC_ACTIVE_HIGH 0x08
  115. #define P2RD_SYNC_CONTROL_VSYNC_INACTIVE 0x20
  116. #define P2RD_SYNC_CONTROL_HSYNC_ACTIVE_LOW 0x00
  117. #define P2RD_SYNC_CONTROL_HSYNC_ACTIVE_HIGH 0x01
  118. #define P2RD_SYNC_CONTROL_HSYNC_INACTIVE 0x04
  119. #define P2RD_DAC_CONTROL_BLANK_PEDESTAL_ENABLED 0x80
  120. #define P2RD_PIXEL_SIZE_8BPP 0x00
  121. #define P2RD_PIXEL_SIZE_16BPP 0x01
  122. #define P2RD_PIXEL_SIZE_24_BPP 0x04
  123. #define P2RD_PIXEL_SIZE_32BPP 0x02
  124. #define P2RD_COLOR_FORMAT_CI8 0x0e
  125. #define P2RD_COLOR_FORMAT_8BPP 0x05
  126. #define P2RD_COLOR_FORMAT_15BPP 0x01
  127. #define P2RD_COLOR_FORMAT_16BPP 0x10
  128. #define P2RD_COLOR_FORMAT_32BPP 0x00
  129. #define P2RD_COLOR_FORMAT_LINEAR_EXT 0x40
  130. #define P2RD_COLOR_FORMAT_RGB 0x20
  131. #define P2RD_CURSOR_MODE_REVERSE 0x40
  132. #define P2RD_CURSOR_MODE_WINDOWS 0x00
  133. #define P2RD_CURSOR_MODE_X 0x10
  134. #define P2RD_CURSOR_MODE_3COLOR 0x20
  135. #define P2RD_CURSOR_MODE_15COLOR 0x30
  136. #define P2RD_CURSOR_MODE_64x64 0x00
  137. #define P2RD_CURSOR_MODE_P0_32x32x2 0x02
  138. #define P2RD_CURSOR_MODE_P1_32x32x2 0x04
  139. #define P2RD_CURSOR_MODE_P2_32x32x2 0x06
  140. #define P2RD_CURSOR_MODE_P3_32x32x2 0x08
  141. #define P2RD_CURSOR_MODE_P01_32x32x4 0x0a
  142. #define P2RD_CURSOR_MODE_P23_32x32x4 0x0c
  143. #define P2RD_CURSOR_MODE_ENABLED 0x01
  144. #define P2RD_CURSOR_CONTROL_RPOS_ENABLED 0x04
  145. #define P2RD_CURSOR_CONTROL_DOUBLE_Y 0x02
  146. #define P2RD_CURSOR_CONTROL_DOUBLE_X 0x01
  147. #define P2RD_DCLK_CONTROL_LOCKED 0x02 // read-only
  148. #define P2RD_DCLK_CONTROL_ENABLED 0x01
  149. #define P2RD_DCLK_CONTROL_RUN 0x08
  150. #define P2RD_MCLK_CONTROL_LOCKED 0x02 // read-only
  151. #define P2RD_MCLK_CONTROL_ENABLED 0x01
  152. #define P2RD_MCLK_CONTROL_RUN 0x08
  153. #define P2RD_CURSOR_PALETTE_CURSOR_RGB(RGBIndex, Red, Green, Blue) \
  154. { \
  155. P2RD_LOAD_INDEX_REG(P2RD_CURSOR_PALETTE_START+3*(int)RGBIndex+0, Red); \
  156. P2RD_LOAD_INDEX_REG(P2RD_CURSOR_PALETTE_START+3*(int)RGBIndex+1, Green); \
  157. P2RD_LOAD_INDEX_REG(P2RD_CURSOR_PALETTE_START+3*(int)RGBIndex+2, Blue); \
  158. }
  159. #if 0
  160. //
  161. // need a delay between each write to the P2RD. The only way to guarantee
  162. // that the write has completed is to read from a Permedia 2 control register.
  163. // Reading forces any posted writes to be flushed out.
  164. //
  165. #define P2RD_DELAY \
  166. { \
  167. volatile LONG __junk; \
  168. __junk = VideoPortReadRegisterUlong (FB_MODE_SEL); \
  169. __junk = VideoPortReadRegisterUlong (FB_MODE_SEL); \
  170. }
  171. #else
  172. #define P2RD_DELAY
  173. #endif
  174. //
  175. // macro to load a given data value into an internal P2RD register. The
  176. // second macro loads an internal index register assuming that we have
  177. // already zeroed the high address register.
  178. //
  179. #define P2RD_INDEX_REG(index) \
  180. { \
  181. DEBUG_PRINT((3, "*(0x%x) <-- 0x%x\n", P2RD_INDEX_ADDR_LO, (index) & 0xff)); \
  182. VideoPortWriteRegisterUlong(P2RD_INDEX_ADDR_LO, (ULONG)((index) & 0xff)); \
  183. P2RD_DELAY; \
  184. DEBUG_PRINT((3, "*(0x%x) <-- 0x%x\n", P2RD_INDEX_ADDR_HI, (index) >> 8)); \
  185. VideoPortWriteRegisterUlong(P2RD_INDEX_ADDR_HI, (ULONG)((index) >> 8)); \
  186. P2RD_DELAY; \
  187. }
  188. #define P2RD_LOAD_DATA(data) \
  189. { \
  190. VideoPortWriteRegisterUlong(P2RD_INDEX_DATA, (ULONG)((data) & 0xff)); \
  191. P2RD_DELAY; \
  192. }
  193. #define P2RD_LOAD_INDEX_REG(index, data) \
  194. { \
  195. P2RD_INDEX_REG(index); \
  196. DEBUG_PRINT((3, "*(0x%x) <-- 0x%x\n", P2RD_INDEX_DATA, (data) & 0xff)); \
  197. VideoPortWriteRegisterUlong(P2RD_INDEX_DATA, (ULONG)((data) & 0xff)); \
  198. P2RD_DELAY; \
  199. }
  200. #define P2RD_READ_INDEX_REG(index, data) \
  201. { \
  202. P2RD_INDEX_REG(index); \
  203. data = VideoPortReadRegisterUlong(P2RD_INDEX_DATA) & 0xff; \
  204. P2RD_DELAY; \
  205. DEBUG_PRINT((3, "0x%x <-- *(0x%x)\n", data, P2RD_INDEX_DATA)); \
  206. }
  207. #define P2RD_LOAD_INDEX_REG_LO(index, data) \
  208. { \
  209. VideoPortWriteRegisterUlong(P2RD_INDEX_ADDR_LO, (ULONG)(index)); \
  210. P2RD_DELAY; \
  211. VideoPortWriteRegisterUlong(P2RD_INDEX_DATA, (ULONG)(data)); \
  212. P2RD_DELAY; \
  213. }
  214. //
  215. // macros to load a given RGB triple into the P2RD palette. Send the starting
  216. // index and then send RGB triples. Auto-increment is turned on.
  217. // Use P2RD_PALETTE_START and multiple P2RD_LOAD_PALETTE calls to load
  218. // a contiguous set of entries. Use P2RD_LOAD_PALETTE_INDEX to load a set
  219. // of sparse entries.
  220. //
  221. #define P2RD_PALETTE_START_WR(index) \
  222. { \
  223. VideoPortWriteRegisterUlong(P2RD_PAL_WR_ADDR, (ULONG)(index)); \
  224. P2RD_DELAY; \
  225. }
  226. #define P2RD_PALETTE_START_RD(index) \
  227. { \
  228. VideoPortWriteRegisterUlong(P2RD_PAL_RD_ADDR, (ULONG)(index)); \
  229. P2RD_DELAY; \
  230. }
  231. #define P2RD_LOAD_PALETTE(red, green, blue) \
  232. { \
  233. VideoPortWriteRegisterUlong(P2RD_PAL_DATA, (ULONG)(red)); \
  234. P2RD_DELAY; \
  235. VideoPortWriteRegisterUlong(P2RD_PAL_DATA, (ULONG)(green)); \
  236. P2RD_DELAY; \
  237. VideoPortWriteRegisterUlong(P2RD_PAL_DATA, (ULONG)(blue)); \
  238. P2RD_DELAY; \
  239. }
  240. #define P2RD_LOAD_PALETTE_INDEX(index, red, green, blue) \
  241. { \
  242. VideoPortWriteRegisterUlong(P2RD_PAL_WR_ADDR, (ULONG)(index)); \
  243. P2RD_DELAY; \
  244. VideoPortWriteRegisterUlong(P2RD_PAL_DATA, (ULONG)(red)); \
  245. P2RD_DELAY; \
  246. VideoPortWriteRegisterUlong(P2RD_PAL_DATA, (ULONG)(green)); \
  247. P2RD_DELAY; \
  248. VideoPortWriteRegisterUlong(P2RD_PAL_DATA, (ULONG)(blue)); \
  249. P2RD_DELAY; \
  250. }
  251. //
  252. // macro to read back a given RGB triple from the P2RD palette. Use after
  253. // a call to P2RD_PALETTE_START_RD
  254. //
  255. #define P2RD_READ_PALETTE(red, green, blue) \
  256. { \
  257. red = (UCHAR)(VideoPortReadRegisterUlong(P2RD_PAL_DATA) & 0xff); \
  258. P2RD_DELAY; \
  259. green = (UCHAR)(VideoPortReadRegisterUlong(P2RD_PAL_DATA) & 0xff); \
  260. P2RD_DELAY; \
  261. blue = (UCHAR)(VideoPortReadRegisterUlong(P2RD_PAL_DATA) & 0xff); \
  262. P2RD_DELAY; \
  263. }
  264. //
  265. // macros to set/get the pixel read mask. The mask is 8 bits wide and gets
  266. // replicated across all bytes that make up a pixel.
  267. //
  268. #define P2RD_SET_PIXEL_READMASK(mask) \
  269. { \
  270. VideoPortWriteRegisterUlong(P2RD_PIXEL_MASK, (ULONG)(mask)); \
  271. P2RD_DELAY; \
  272. }
  273. #define P2RD_READ_PIXEL_READMASK(mask) \
  274. { \
  275. mask = VideoPortReadRegisterUlong(P2RD_PIXEL_MASK) & 0xff; \
  276. }
  277. //
  278. // macros to load values into the cursor array usage is P2RD_CURSOR_ARRAR_START() followed by
  279. // n iterations of P2RD_LOAD_CURSOR_ARRAY() or P2RD_READ_CURSOR_ARRAY()
  280. //
  281. #define P2RD_CURSOR_ARRAY_START(offset) \
  282. { \
  283. P2RD_DELAY; \
  284. VideoPortWriteRegisterUlong(P2RD_INDEX_ADDR_LO, (ULONG)(((offset)+P2RD_CURSOR_PATTERN_START) & 0xff)); \
  285. P2RD_DELAY; \
  286. VideoPortWriteRegisterUlong(P2RD_INDEX_ADDR_HI, (ULONG)(((offset)+P2RD_CURSOR_PATTERN_START) >> 8)); \
  287. P2RD_DELAY; \
  288. }
  289. #define P2RD_LOAD_CURSOR_ARRAY(data) \
  290. { \
  291. VideoPortWriteRegisterUlong(P2RD_INDEX_DATA, (ULONG)(data)); \
  292. P2RD_DELAY; \
  293. }
  294. #define P2RD_READ_CURSOR_ARRAY(data) \
  295. { \
  296. data = VideoPortReadRegisterUlong(P2RD_INDEX_DATA) & 0xff; \
  297. P2RD_DELAY; \
  298. }
  299. //
  300. // macro to move the cursor
  301. //
  302. #define P2RD_MOVE_CURSOR(x, y) \
  303. { \
  304. VideoPortWriteRegisterUlong(P2RD_INDEX_ADDR_HI, (ULONG)0); \
  305. P2RD_DELAY; \
  306. P2RD_LOAD_INDEX_REG_LO(P2RD_CURSOR_X_LOW, (ULONG)((x) & 0xff)); \
  307. P2RD_LOAD_INDEX_REG_LO(P2RD_CURSOR_X_HIGH, (ULONG)((x) >> 8)); \
  308. P2RD_LOAD_INDEX_REG_LO(P2RD_CURSOR_Y_LOW, (ULONG)((y) & 0xff)); \
  309. P2RD_LOAD_INDEX_REG_LO(P2RD_CURSOR_Y_HIGH, (ULONG)((y) >> 8)); \
  310. }
  311. //
  312. // macro to change the cursor hotspot
  313. //
  314. #define P2RD_CURSOR_HOTSPOT(x, y) \
  315. { \
  316. VideoPortWriteRegisterUlong(P2RD_INDEX_ADDR_HI, (ULONG)(0)); \
  317. P2RD_DELAY; \
  318. P2RD_LOAD_INDEX_REG_LO(P2RD_CURSOR_HOTSPOT_X, (ULONG)(x)); \
  319. P2RD_LOAD_INDEX_REG_LO(P2RD_CURSOR_HOTSPOT_Y, (ULONG)(y)); \
  320. }
  321. //
  322. // macro to change the cursor color
  323. //
  324. #define P2RD_CURSOR_COLOR(red, green, blue) \
  325. { \
  326. VideoPortWriteRegisterUlong(P2RD_INDEX_ADDR_HI, (ULONG)(0)); \
  327. P2RD_DELAY; \
  328. P2RD_LOAD_INDEX_REG_LO(P2RD_CURSOR_HOTSPOT_X, (ULONG)(x)); \
  329. P2RD_LOAD_INDEX_REG_LO(P2RD_CURSOR_HOTSPOT_Y, (ULONG)(y)); \
  330. }