Leaked source code of windows server 2003
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  1. /******************************Module*Header*******************************\
  2. *
  3. * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
  4. * !! !!
  5. * !! WARNING: NOT DDK SAMPLE CODE !!
  6. * !! !!
  7. * !! This source code is provided for completeness only and should not be !!
  8. * !! used as sample code for display driver development. Only those sources !!
  9. * !! marked as sample code for a given driver component should be used for !!
  10. * !! development purposes. !!
  11. * !! !!
  12. * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
  13. *
  14. * Module Name: dma.h
  15. *
  16. * Content: DMA transport definitons and macros
  17. *
  18. * Copyright (c) 1994-1999 3Dlabs Inc. Ltd. All rights reserved.
  19. * Copyright (c) 1995-2003 Microsoft Corporation. All rights reserved.
  20. \*****************************************************************************/
  21. #ifndef __DMA_H
  22. #define __DMA_H
  23. //-----------------------------------------------------------------------------
  24. //
  25. // DMA/Fifo utility function declarations
  26. //
  27. //-----------------------------------------------------------------------------
  28. // Enables a driver to switch between FIFO/DMA operations
  29. void HWC_SwitchToFIFO( P3_THUNKEDDATA* pThisDisplay, LPGLINTINFO pGLInfo );
  30. void HWC_SwitchToDMA( P3_THUNKEDDATA* pThisDisplay, LPGLINTINFO pGLInfo );
  31. void HWC_AllocDMABuffer(P3_THUNKEDDATA* pThisDisplay);
  32. DWORD WINAPI HWC_StartDMA(P3_THUNKEDDATA* pThisDisplay,
  33. DWORD dwContext,
  34. DWORD dwSize,
  35. DWORD dwPhys,
  36. ULONG_PTR dwVirt,
  37. DWORD dwEvent);
  38. void HWC_GetDXBuffer( P3_THUNKEDDATA*, char*, int );
  39. void HWC_SetDXBuffer( P3_THUNKEDDATA*, char*, int );
  40. void HWC_FlushDXBuffer( P3_THUNKEDDATA* );
  41. //-----------------------------------------------------------------------------
  42. //
  43. // DMA & Fifo common definitions & macros
  44. //
  45. //-----------------------------------------------------------------------------
  46. // Compute the depth of the FIFO depending on if we are a simple
  47. // Permedia3 or if we are going through the Gamma chip of the GVX1
  48. #define FIFO_DEPTH ((ULONG)((TLCHIP_GAMMA) ? 32 : 120))
  49. // Always check the FIFO. Remember that the DMA just loads the FIFO, and even
  50. // if the DMA is empty, there can be tons left in the FIFO.
  51. #define DRAW_ENGINE_BUSY(pThisDisplay) \
  52. ( pThisDisplay->pGlint->InFIFOSpace < FIFO_DEPTH )
  53. // We track the fifo space so that we never wait for entries that we don't
  54. // need to. We wait for nEntries + 1 instead of nEntries because of an issue
  55. // in the Gamma chip
  56. #define __WAIT_GLINT_FIFO_SPACE(nEntries) \
  57. { \
  58. DWORD dwEntries; \
  59. do \
  60. { \
  61. dwEntries = *inFIFOptr; \
  62. if (dwEntries > 120) dwEntries = 120; \
  63. } while (dwEntries < nEntries + 1); \
  64. }
  65. // Local variables needed on all DX functions that try to use DMA/FIFO
  66. #define P3_DMA_DEFS() \
  67. ULONG * volatile dmaPtr; \
  68. ULONG * volatile inFIFOptr = \
  69. (ULONG *)(&pThisDisplay->pGlint->InFIFOSpace)
  70. // Debug & free versions to get / commit / flush a buffer
  71. #if DBG
  72. #define P3_DMA_GET_BUFFER() \
  73. { \
  74. HWC_GetDXBuffer( pThisDisplay, __FILE__, __LINE__ ); \
  75. dmaPtr = pThisDisplay->pGLInfo->CurrentBuffer; \
  76. }
  77. #define P3_DMA_COMMIT_BUFFER() \
  78. { \
  79. pThisDisplay->pGLInfo->CurrentBuffer = dmaPtr; \
  80. HWC_SetDXBuffer( pThisDisplay, __FILE__, __LINE__ ); \
  81. }
  82. #else
  83. #define P3_DMA_GET_BUFFER() \
  84. dmaPtr = pThisDisplay->pGLInfo->CurrentBuffer;
  85. #define P3_DMA_COMMIT_BUFFER() \
  86. { \
  87. pThisDisplay->pGLInfo->CurrentBuffer = dmaPtr; \
  88. }
  89. #endif // DBG
  90. #define P3_DMA_FLUSH_BUFFER() \
  91. { \
  92. P3_DMA_COMMIT_BUFFER(); \
  93. HWC_FlushDXBuffer( pThisDisplay ); \
  94. dmaPtr = pThisDisplay->pGLInfo->CurrentBuffer; \
  95. }
  96. #if DBG
  97. #define __SET_FIFO_ENTRIES_LEFT(a) \
  98. do { \
  99. g_pThisTemp = pThisDisplay; \
  100. pThisDisplay->EntriesLeft = (a); \
  101. } while (0)
  102. #define __SET_DMA_ENTRIES_LEFT(a) \
  103. do { \
  104. g_pThisTemp = pThisDisplay; \
  105. pThisDisplay->DMAEntriesLeft = (a); \
  106. } while (0)
  107. #define __RESET_FIFO_ERROR_CHECK g_bDetectedFIFOError = FALSE
  108. #else
  109. #define __SET_FIFO_ENTRIES_LEFT(a)
  110. #define __SET_DMA_ENTRIES_LEFT(a)
  111. #define __RESET_FIFO_ERROR_CHECK
  112. #endif // DBG
  113. #if DBG
  114. // Note the DMAEntriesLeft+=2 compensates for the fact that this macro
  115. // doesn't load a DMA Buffer - it writes to the FIFO directly. That
  116. // means it does need to wait for FIFO space
  117. #define LOAD_GLINT_REG(r, v) \
  118. { \
  119. DISPDBG(( DBGLVL, "LoadGlintReg: %s 0x%x", #r, v )); \
  120. __SET_DMA_ENTRIES_LEFT(pThisDisplay->DMAEntriesLeft + 2); \
  121. CHECK_FIFO(2); \
  122. MEMORY_BARRIER(); \
  123. pThisDisplay->pGlint->r = v; \
  124. MEMORY_BARRIER(); \
  125. }
  126. // Control registers do not require fifo entries
  127. #define LOAD_GLINT_CTRL_REG(r, v) \
  128. { \
  129. MEMORY_BARRIER(); \
  130. pThisDisplay->pGlint->r = v; \
  131. MEMORY_BARRIER(); \
  132. }
  133. #else
  134. #define LOAD_GLINT_REG(r, v) \
  135. { \
  136. MEMORY_BARRIER(); \
  137. pThisDisplay->pGlint->r = v; \
  138. MEMORY_BARRIER(); \
  139. }
  140. #define LOAD_GLINT_CTRL_REG(r, v) \
  141. { \
  142. MEMORY_BARRIER(); \
  143. pThisDisplay->pGlint->r = v; \
  144. MEMORY_BARRIER(); \
  145. }
  146. #endif
  147. #define READ_GLINT_CTRL_REG(r) (pThisDisplay->pGlint->r)
  148. // We wait for nEntries + 1 instead of nEntries because of a bug in Gamma chip
  149. #define WAIT_GLINT_FIFO(nEntries) \
  150. while((READ_GLINT_CTRL_REG (InFIFOSpace)) < nEntries + 1);
  151. #define READ_OUTPUT_FIFO(d) d = READ_GLINT_CTRL_REG(GPFifo[0])
  152. #define GET_DMA_COUNT(c) c = READ_GLINT_CTRL_REG(DMACount)
  153. #if DBG
  154. #define SET_MAX_ERROR_CHECK_FIFO_SPACE pThisDisplay->EntriesLeft = 120;
  155. #define SET_ERROR_CHECK_FIFO_SPACES(a) pThisDisplay->EntriesLeft = (a);
  156. #else
  157. #define SET_MAX_ERROR_CHECK_FIFO_SPACE
  158. #define SET_ERROR_CHECK_FIFO_SPACES(a)
  159. #endif
  160. //-----------------------------------------------------------------------------
  161. //
  162. // DMA EXCLUSIVE definitions & macros
  163. //
  164. // Below macros are used if we have defined that we want a DMA capable build
  165. //-----------------------------------------------------------------------------
  166. #ifdef WANT_DMA
  167. #define WAIT_FIFO(a) \
  168. do { if(pThisDisplay->pGLInfo->InterfaceType != GLINT_DMA) \
  169. __WAIT_GLINT_FIFO_SPACE(a); \
  170. __SET_FIFO_ENTRIES_LEFT(a); \
  171. __RESET_FIFO_ERROR_CHECK; \
  172. } while (0)
  173. #define __ENSURE_DMA_SPACE(entries) \
  174. { \
  175. if (pThisDisplay->pGLInfo->InterfaceType != GLINT_NON_DMA) \
  176. { \
  177. if(((ULONG_PTR)dmaPtr + entries) >= \
  178. (ULONG_PTR)(pThisDisplay->pGLInfo->DMAPartition[pThisDisplay->pGLInfo->CurrentPartition].MaxAddress)) \
  179. { \
  180. P3_DMA_FLUSH_BUFFER(); \
  181. } \
  182. } \
  183. else \
  184. { \
  185. pThisDisplay->pGLInfo->CurrentBuffer = (ULONG*)&pThisDisplay->pGlint->GPFifo; \
  186. dmaPtr = pThisDisplay->pGLInfo->CurrentBuffer; \
  187. } \
  188. __SET_DMA_ENTRIES_LEFT(entries); \
  189. __RESET_FIFO_ERROR_CHECK; \
  190. }
  191. #define P3_ENSURE_DX_SPACE(entries) \
  192. { \
  193. __ENSURE_DMA_SPACE(entries) \
  194. __SET_DMA_ENTRIES_LEFT(entries); \
  195. __RESET_FIFO_ERROR_CHECK; \
  196. }
  197. #if WNT_DDRAW
  198. #define WAIT_DMA_COMPLETE DDWaitDMAComplete(pThisDisplay->ppdev);
  199. #else
  200. extern void Wait_2D_DMA_Complete(P3_THUNKEDDATA* pThisDisplay);
  201. #define PATIENTLY_WAIT_DMA() \
  202. { \
  203. volatile DWORD count; \
  204. while (GET_DMA_COUNT(count) > 0) \
  205. { \
  206. if (count < 32) \
  207. count = 1; \
  208. else \
  209. count <<= 1; \
  210. while (--count > 0) NULL; \
  211. } \
  212. }
  213. #define WAIT_DMA_COMPLETE \
  214. { \
  215. CHECK_ERROR(); \
  216. if (!(pThisDisplay->pGLInfo->GlintBoardStatus & GLINT_DMA_COMPLETE)) { \
  217. if (pThisDisplay->pGLInfo->GlintBoardStatus & GLINT_INTR_CONTEXT) { \
  218. static int retry = 0; \
  219. while (!(pThisDisplay->pGLInfo->GlintBoardStatus & GLINT_DMA_COMPLETE)) \
  220. { \
  221. LOCKUP(); \
  222. } \
  223. } else { \
  224. if (pThisDisplay->pGLInfo->dwCurrentContext == CONTEXT_DISPLAY_HANDLE) {\
  225. Wait_2D_DMA_Complete(pThisDisplay); \
  226. } \
  227. else { \
  228. PATIENTLY_WAIT_DMA(); \
  229. pThisDisplay->pGLInfo->GlintBoardStatus |= GLINT_DMA_COMPLETE; \
  230. } \
  231. } \
  232. ASSERTDD( READ_GLINT_CTRL_REG(DMACount) == 0, "DMACount not zero after WAIT_DMA_COMPLETE" );\
  233. ASSERTDD((READ_GLINT_CTRL_REG(ByDMAControl) & 3 ) == 0, "Bypass DMA not complete after WAIT_DMA_COMPLETE" );\
  234. } \
  235. else { \
  236. ASSERTDD( READ_GLINT_CTRL_REG(DMACount) == 0, "DMACount not zero despite GLINT_DMA_COMPLETE" );\
  237. ASSERTDD((READ_GLINT_CTRL_REG(ByDMAControl) & 3 ) == 0, "Bypass DMA not complete despite GLINT_DMA_COMPLETE" );\
  238. } \
  239. CHECK_ERROR(); \
  240. }
  241. #endif // WNT_DDRAW
  242. #if WNT_DDRAW
  243. #define SYNC_WITH_GLINT \
  244. vNTSyncWith2DDriver(pThisDisplay->ppdev); \
  245. SET_MAX_ERROR_CHECK_FIFO_SPACE
  246. #else
  247. #define SYNC_WITH_GLINT \
  248. DISPDBG(( DBGLVL, "SYNC_WITH_GLINT" )); \
  249. WAIT_DMA_COMPLETE \
  250. while( pThisDisplay->pGlint->InFIFOSpace < 6 ) /* void */ ; \
  251. SET_ERROR_CHECK_FIFO_SPACES(6); \
  252. LOAD_GLINT_REG(FilterMode, 0x400); \
  253. LOAD_GLINT_REG(Sync, 0); \
  254. LOAD_GLINT_REG(FilterMode, 0x0); \
  255. do { \
  256. while (pThisDisplay->pGlint->OutFIFOWords == 0) /* void */ ; \
  257. } while (pThisDisplay->pGlint->GPFifo[0] != 0x188); \
  258. DISPDBG((DBGLVL,"Sync at line %d in %s", __LINE__, __FILE__)); \
  259. SET_MAX_ERROR_CHECK_FIFO_SPACE
  260. #endif // WNT_DDRAW
  261. //-----------------------------------------------------------------------------
  262. //
  263. // FIFO EXCLUSIVE definitions & macros
  264. //
  265. //-----------------------------------------------------------------------------
  266. #else //!WANT_DMA
  267. #define WAIT_FIFO(a) \
  268. do { \
  269. __WAIT_GLINT_FIFO_SPACE(a); \
  270. __SET_FIFO_ENTRIES_LEFT(a); \
  271. __RESET_FIFO_ERROR_CHECK; \
  272. } while(0)
  273. #define P3_ENSURE_DX_SPACE(entries) \
  274. { \
  275. dmaPtr = (unsigned long *) (DWORD)pThisDisplay->pGlint->GPFifo; \
  276. P3_DMA_COMMIT_BUFFER(); \
  277. __SET_DMA_ENTRIES_LEFT(entries); \
  278. __RESET_FIFO_ERROR_CHECK; \
  279. }
  280. #define P3_DMA_FLUSH_BUFFER() \
  281. { \
  282. dmaPtr = (unsigned long *) pThisDisplay->pGlint->GPFifo; \
  283. P3_DMA_COMMIT_BUFFER(); \
  284. }
  285. #define WAIT_DMA_COMPLETE
  286. #define SYNC_WITH_GLINT \
  287. vNTSyncWith2DDriver(pThisDisplay->ppdev); \
  288. SET_MAX_ERROR_CHECK_FIFO_SPACE
  289. #endif // !WANT_DMA
  290. //-----------------------------------------------------------------------------
  291. //
  292. // Win9x specific definitons & macros
  293. //
  294. //-----------------------------------------------------------------------------
  295. #if W95_DDRAW
  296. // wait for DMA to complete (DMACount becomes zero). So as not to kill the
  297. // PCI bus bandwidth for the DMA put in a backoff based on the amount of data
  298. // still left to DMA. Also set the timer going if at any time, the count we
  299. // read is the same as the previous count.
  300. //
  301. #if DBG
  302. #define LOCKUP() \
  303. if(( ++retry & 0xfffff ) == 0 ) \
  304. { \
  305. DISPDBG(( WRNLVL, "Locked up in WAIT_DMA_COMPLETE" \
  306. " - %d retries", retry )); \
  307. }
  308. #else
  309. #define LOCKUP()
  310. #endif
  311. #endif // W95_DDRAW
  312. //-----------------------------------------------------------------------------
  313. //
  314. // Macros used to send data to the Permedia 3 hardware
  315. //
  316. //-----------------------------------------------------------------------------
  317. #define SEND_P3_DATA(tag,data) \
  318. { \
  319. MEMORY_BARRIER(); \
  320. dmaPtr[0] = tag##_Tag; \
  321. MEMORY_BARRIER(); \
  322. dmaPtr[1] = data; \
  323. MEMORY_BARRIER(); \
  324. dmaPtr+=2; \
  325. CHECK_FIFO(2); \
  326. }
  327. #define SEND_P3_DATA_OFFSET(tag,data, i) \
  328. { \
  329. MEMORY_BARRIER(); \
  330. dmaPtr[0] = (tag##_Tag + i); \
  331. MEMORY_BARRIER(); \
  332. dmaPtr[1] = data; \
  333. MEMORY_BARRIER(); \
  334. dmaPtr += 2; CHECK_FIFO(2); \
  335. }
  336. #define COPY_P3_DATA(tag,data) \
  337. { \
  338. MEMORY_BARRIER(); \
  339. dmaPtr[0] = tag##_Tag; \
  340. MEMORY_BARRIER(); \
  341. dmaPtr[1] = *((unsigned long*) &(data)); \
  342. MEMORY_BARRIER(); \
  343. dmaPtr += 2; \
  344. CHECK_FIFO(2); \
  345. }
  346. #define COPY_P3_DATA_OFFSET(tag,data,i) \
  347. { \
  348. MEMORY_BARRIER(); \
  349. dmaPtr[0] = tag##_Tag + i; \
  350. MEMORY_BARRIER(); \
  351. dmaPtr[1] = *((unsigned long*) &(data)); \
  352. MEMORY_BARRIER(); \
  353. dmaPtr += 2; \
  354. CHECK_FIFO(2); \
  355. }
  356. #define P3RX_HOLD_CMD(tag, count) \
  357. { \
  358. MEMORY_BARRIER(); \
  359. dmaPtr[0] = ( tag##_Tag | ((count-1) << 16)); \
  360. dmaPtr++; \
  361. CHECK_FIFO(1); \
  362. }
  363. #define P3_DMA_GET_BUFFER_ENTRIES( fifo_count ) \
  364. { \
  365. P3_DMA_GET_BUFFER(); \
  366. WAIT_FIFO( fifo_count ); \
  367. P3_ENSURE_DX_SPACE((fifo_count)); \
  368. }
  369. #define ADD_FUNNY_DWORD(a) \
  370. { \
  371. MEMORY_BARRIER(); \
  372. *dmaPtr++ = a; \
  373. MEMORY_BARRIER(); \
  374. CHECK_FIFO(1); \
  375. }
  376. //-----------------------------------------------------------------------------
  377. //
  378. // Setup/Clear discconnect signals
  379. //
  380. // Setting the FIFODiscon register to 1 forces host write retries until
  381. // the data is accepted (might affect other time-critical processes though)
  382. //
  383. //-----------------------------------------------------------------------------
  384. #if DBG
  385. #define NO_FIFO_CHECK pThisDisplay->EntriesLeft = -20000;
  386. #define END_NO_FIFO_CHECK pThisDisplay->EntriesLeft = 0;
  387. #else
  388. #define NO_FIFO_CHECK
  389. #define END_NO_FIFO_CHECK
  390. #endif
  391. #define SET_DISCONNECT_CONTROL(val) \
  392. if(pThisDisplay->pGLInfo->InterfaceType == GLINT_NON_DMA) \
  393. { \
  394. WAIT_FIFO(1); \
  395. if(pThisDisplay->pGLInfo->dwFlags & GMVF_DELTA) \
  396. { \
  397. LOAD_GLINT_REG(DeltaDisconnectControl,val); \
  398. } \
  399. else \
  400. { \
  401. LOAD_GLINT_REG(FIFODiscon,val); \
  402. } \
  403. }
  404. #define TURN_ON_DISCONNECT \
  405. SET_DISCONNECT_CONTROL(0x1) \
  406. NO_FIFO_CHECK
  407. #define TURN_OFF_DISCONNECT \
  408. SET_DISCONNECT_CONTROL(0x0) \
  409. END_NO_FIFO_CHECK
  410. #define SET_D3D_DISCONNECT_CONTROL(val) \
  411. if(pThisDisplay->pGLInfo->InterfaceType == GLINT_NON_DMA) \
  412. { \
  413. WAIT_FIFO(1); \
  414. if(pThisDisplay->pGLInfo->dwFlags & GMVF_DELTA) \
  415. { \
  416. LOAD_GLINT_REG(DeltaDisconnectControl,val); \
  417. } \
  418. else \
  419. { \
  420. LOAD_GLINT_REG(FIFODiscon,val); \
  421. } \
  422. }
  423. #define TURN_ON_D3D_DISCONNECT \
  424. SET_D3D_DISCONNECT_CONTROL(0x1) \
  425. NO_FIFO_CHECK
  426. #define TURN_OFF_D3D_DISCONNECT \
  427. SET_D3D_DISCONNECT_CONTROL(0x0) \
  428. END_NO_FIFO_CHECK
  429. //-----------------------------------------------------------------------------
  430. //
  431. // Macros used to switch the chips hardware context between DDRAW/D3D ops
  432. //
  433. //-----------------------------------------------------------------------------
  434. #define DDRAW_OPERATION(pContext, pThisDisplay) \
  435. { \
  436. ASSERTDD(pThisDisplay, "Error: pThisDisplay invalid in DDRAW_OPERATION!");\
  437. if (!IS_DXCONTEXT_CURRENT(pThisDisplay)) \
  438. { \
  439. DXCONTEXT_IMMEDIATE(pThisDisplay); \
  440. if (pThisDisplay->b2D_FIFOS == TRUE) \
  441. { \
  442. HWC_SwitchToFIFO(pThisDisplay, pThisDisplay->pGLInfo); \
  443. } \
  444. else \
  445. { \
  446. HWC_SwitchToDMA(pThisDisplay, pThisDisplay->pGLInfo); \
  447. } \
  448. HWC_SwitchToDDRAW(pThisDisplay, TRUE); \
  449. pThisDisplay->pGLInfo->dwDirectXState = DIRECTX_LASTOP_2D; \
  450. } \
  451. else \
  452. { \
  453. if (pThisDisplay->pGLInfo->dwDirectXState != DIRECTX_LASTOP_2D) \
  454. { \
  455. if (pThisDisplay->b2D_FIFOS == TRUE) \
  456. { \
  457. HWC_SwitchToFIFO(pThisDisplay, pThisDisplay->pGLInfo); \
  458. } \
  459. else \
  460. { \
  461. HWC_SwitchToDMA(pThisDisplay, pThisDisplay->pGLInfo); \
  462. } \
  463. HWC_SwitchToDDRAW(pThisDisplay, FALSE); \
  464. pThisDisplay->pGLInfo->dwDirectXState = DIRECTX_LASTOP_2D; \
  465. } \
  466. } \
  467. }
  468. #define D3D_OPERATION(pContext, pThisDisplay) \
  469. { \
  470. ASSERTDD(pThisDisplay, "Error: pThisDisplay invalid in D3D_OPERATION!"); \
  471. ASSERTDD(pContext, "Error: pContext invalid in D3D_OPERATION!"); \
  472. if (!IS_DXCONTEXT_CURRENT(pThisDisplay)) \
  473. { \
  474. DXCONTEXT_IMMEDIATE(pThisDisplay); \
  475. if (pContext->b3D_FIFOS == TRUE) \
  476. { \
  477. HWC_SwitchToFIFO(pThisDisplay, pThisDisplay->pGLInfo); \
  478. } \
  479. else \
  480. { \
  481. HWC_SwitchToDMA(pThisDisplay, pThisDisplay->pGLInfo); \
  482. } \
  483. HWC_SwitchToD3D(pContext, pThisDisplay, TRUE); \
  484. pThisDisplay->pGLInfo->dwDirectXState = (ULONG_PTR)pContext; \
  485. } \
  486. else \
  487. { \
  488. if ((pThisDisplay->pGLInfo->dwDirectXState != (ULONG_PTR)pContext) || \
  489. (pContext->dwDirtyFlags & CONTEXT_DIRTY_RENDER_OFFSETS)) \
  490. { \
  491. if (pContext->b3D_FIFOS == TRUE) \
  492. { \
  493. HWC_SwitchToFIFO(pThisDisplay, pThisDisplay->pGLInfo); \
  494. } \
  495. else \
  496. { \
  497. HWC_SwitchToDMA(pThisDisplay, pThisDisplay->pGLInfo); \
  498. } \
  499. HWC_SwitchToD3D(pContext, pThisDisplay, FALSE); \
  500. pThisDisplay->pGLInfo->dwDirectXState = (ULONG_PTR)pContext; \
  501. } \
  502. } \
  503. }
  504. // Function to update the DDDRAW & D3D Software copy
  505. void HWC_SwitchToDDRAW( P3_THUNKEDDATA* pThisDisplay, BOOL bDXEntry );
  506. void HWC_SwitchToD3D(struct _p3_d3dcontext* pContext,
  507. struct tagThunkedData* pThisDisplay, BOOL bDXEntry);
  508. #endif __DMA_H