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599 lines
27 KiB
599 lines
27 KiB
/******************************Module*Header*******************************\
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*
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* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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* !! !!
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* !! WARNING: NOT DDK SAMPLE CODE !!
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* !! !!
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* !! This source code is provided for completeness only and should not be !!
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* !! used as sample code for display driver development. Only those sources !!
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* !! marked as sample code for a given driver component should be used for !!
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* !! development purposes. !!
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* !! !!
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* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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*
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* Module Name: dma.h
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*
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* Content: DMA transport definitons and macros
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*
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* Copyright (c) 1994-1999 3Dlabs Inc. Ltd. All rights reserved.
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* Copyright (c) 1995-2003 Microsoft Corporation. All rights reserved.
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\*****************************************************************************/
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#ifndef __DMA_H
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#define __DMA_H
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//-----------------------------------------------------------------------------
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//
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// DMA/Fifo utility function declarations
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//
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//-----------------------------------------------------------------------------
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// Enables a driver to switch between FIFO/DMA operations
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void HWC_SwitchToFIFO( P3_THUNKEDDATA* pThisDisplay, LPGLINTINFO pGLInfo );
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void HWC_SwitchToDMA( P3_THUNKEDDATA* pThisDisplay, LPGLINTINFO pGLInfo );
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void HWC_AllocDMABuffer(P3_THUNKEDDATA* pThisDisplay);
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DWORD WINAPI HWC_StartDMA(P3_THUNKEDDATA* pThisDisplay,
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DWORD dwContext,
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DWORD dwSize,
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DWORD dwPhys,
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ULONG_PTR dwVirt,
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DWORD dwEvent);
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void HWC_GetDXBuffer( P3_THUNKEDDATA*, char*, int );
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void HWC_SetDXBuffer( P3_THUNKEDDATA*, char*, int );
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void HWC_FlushDXBuffer( P3_THUNKEDDATA* );
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//-----------------------------------------------------------------------------
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//
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// DMA & Fifo common definitions & macros
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//
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//-----------------------------------------------------------------------------
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// Compute the depth of the FIFO depending on if we are a simple
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// Permedia3 or if we are going through the Gamma chip of the GVX1
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#define FIFO_DEPTH ((ULONG)((TLCHIP_GAMMA) ? 32 : 120))
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// Always check the FIFO. Remember that the DMA just loads the FIFO, and even
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// if the DMA is empty, there can be tons left in the FIFO.
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#define DRAW_ENGINE_BUSY(pThisDisplay) \
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( pThisDisplay->pGlint->InFIFOSpace < FIFO_DEPTH )
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// We track the fifo space so that we never wait for entries that we don't
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// need to. We wait for nEntries + 1 instead of nEntries because of an issue
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// in the Gamma chip
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#define __WAIT_GLINT_FIFO_SPACE(nEntries) \
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{ \
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DWORD dwEntries; \
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do \
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{ \
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dwEntries = *inFIFOptr; \
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if (dwEntries > 120) dwEntries = 120; \
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} while (dwEntries < nEntries + 1); \
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}
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// Local variables needed on all DX functions that try to use DMA/FIFO
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#define P3_DMA_DEFS() \
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ULONG * volatile dmaPtr; \
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ULONG * volatile inFIFOptr = \
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(ULONG *)(&pThisDisplay->pGlint->InFIFOSpace)
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// Debug & free versions to get / commit / flush a buffer
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#if DBG
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#define P3_DMA_GET_BUFFER() \
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{ \
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HWC_GetDXBuffer( pThisDisplay, __FILE__, __LINE__ ); \
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dmaPtr = pThisDisplay->pGLInfo->CurrentBuffer; \
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}
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#define P3_DMA_COMMIT_BUFFER() \
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{ \
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pThisDisplay->pGLInfo->CurrentBuffer = dmaPtr; \
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HWC_SetDXBuffer( pThisDisplay, __FILE__, __LINE__ ); \
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}
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#else
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#define P3_DMA_GET_BUFFER() \
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dmaPtr = pThisDisplay->pGLInfo->CurrentBuffer;
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#define P3_DMA_COMMIT_BUFFER() \
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{ \
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pThisDisplay->pGLInfo->CurrentBuffer = dmaPtr; \
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}
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#endif // DBG
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#define P3_DMA_FLUSH_BUFFER() \
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{ \
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P3_DMA_COMMIT_BUFFER(); \
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HWC_FlushDXBuffer( pThisDisplay ); \
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dmaPtr = pThisDisplay->pGLInfo->CurrentBuffer; \
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}
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#if DBG
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#define __SET_FIFO_ENTRIES_LEFT(a) \
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do { \
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g_pThisTemp = pThisDisplay; \
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pThisDisplay->EntriesLeft = (a); \
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} while (0)
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#define __SET_DMA_ENTRIES_LEFT(a) \
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do { \
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g_pThisTemp = pThisDisplay; \
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pThisDisplay->DMAEntriesLeft = (a); \
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} while (0)
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#define __RESET_FIFO_ERROR_CHECK g_bDetectedFIFOError = FALSE
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#else
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#define __SET_FIFO_ENTRIES_LEFT(a)
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#define __SET_DMA_ENTRIES_LEFT(a)
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#define __RESET_FIFO_ERROR_CHECK
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#endif // DBG
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#if DBG
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// Note the DMAEntriesLeft+=2 compensates for the fact that this macro
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// doesn't load a DMA Buffer - it writes to the FIFO directly. That
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// means it does need to wait for FIFO space
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#define LOAD_GLINT_REG(r, v) \
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{ \
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DISPDBG(( DBGLVL, "LoadGlintReg: %s 0x%x", #r, v )); \
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__SET_DMA_ENTRIES_LEFT(pThisDisplay->DMAEntriesLeft + 2); \
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CHECK_FIFO(2); \
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MEMORY_BARRIER(); \
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pThisDisplay->pGlint->r = v; \
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MEMORY_BARRIER(); \
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}
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// Control registers do not require fifo entries
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#define LOAD_GLINT_CTRL_REG(r, v) \
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{ \
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MEMORY_BARRIER(); \
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pThisDisplay->pGlint->r = v; \
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MEMORY_BARRIER(); \
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}
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#else
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#define LOAD_GLINT_REG(r, v) \
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{ \
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MEMORY_BARRIER(); \
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pThisDisplay->pGlint->r = v; \
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MEMORY_BARRIER(); \
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}
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#define LOAD_GLINT_CTRL_REG(r, v) \
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{ \
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MEMORY_BARRIER(); \
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pThisDisplay->pGlint->r = v; \
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MEMORY_BARRIER(); \
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}
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#endif
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#define READ_GLINT_CTRL_REG(r) (pThisDisplay->pGlint->r)
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// We wait for nEntries + 1 instead of nEntries because of a bug in Gamma chip
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#define WAIT_GLINT_FIFO(nEntries) \
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while((READ_GLINT_CTRL_REG (InFIFOSpace)) < nEntries + 1);
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#define READ_OUTPUT_FIFO(d) d = READ_GLINT_CTRL_REG(GPFifo[0])
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#define GET_DMA_COUNT(c) c = READ_GLINT_CTRL_REG(DMACount)
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#if DBG
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#define SET_MAX_ERROR_CHECK_FIFO_SPACE pThisDisplay->EntriesLeft = 120;
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#define SET_ERROR_CHECK_FIFO_SPACES(a) pThisDisplay->EntriesLeft = (a);
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#else
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#define SET_MAX_ERROR_CHECK_FIFO_SPACE
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#define SET_ERROR_CHECK_FIFO_SPACES(a)
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#endif
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//-----------------------------------------------------------------------------
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//
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// DMA EXCLUSIVE definitions & macros
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//
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// Below macros are used if we have defined that we want a DMA capable build
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//-----------------------------------------------------------------------------
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#ifdef WANT_DMA
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#define WAIT_FIFO(a) \
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do { if(pThisDisplay->pGLInfo->InterfaceType != GLINT_DMA) \
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__WAIT_GLINT_FIFO_SPACE(a); \
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__SET_FIFO_ENTRIES_LEFT(a); \
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__RESET_FIFO_ERROR_CHECK; \
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} while (0)
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#define __ENSURE_DMA_SPACE(entries) \
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{ \
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if (pThisDisplay->pGLInfo->InterfaceType != GLINT_NON_DMA) \
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{ \
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if(((ULONG_PTR)dmaPtr + entries) >= \
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(ULONG_PTR)(pThisDisplay->pGLInfo->DMAPartition[pThisDisplay->pGLInfo->CurrentPartition].MaxAddress)) \
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{ \
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P3_DMA_FLUSH_BUFFER(); \
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} \
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} \
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else \
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{ \
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pThisDisplay->pGLInfo->CurrentBuffer = (ULONG*)&pThisDisplay->pGlint->GPFifo; \
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dmaPtr = pThisDisplay->pGLInfo->CurrentBuffer; \
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} \
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__SET_DMA_ENTRIES_LEFT(entries); \
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__RESET_FIFO_ERROR_CHECK; \
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}
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#define P3_ENSURE_DX_SPACE(entries) \
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{ \
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__ENSURE_DMA_SPACE(entries) \
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__SET_DMA_ENTRIES_LEFT(entries); \
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__RESET_FIFO_ERROR_CHECK; \
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}
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#if WNT_DDRAW
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#define WAIT_DMA_COMPLETE DDWaitDMAComplete(pThisDisplay->ppdev);
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#else
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extern void Wait_2D_DMA_Complete(P3_THUNKEDDATA* pThisDisplay);
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#define PATIENTLY_WAIT_DMA() \
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{ \
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volatile DWORD count; \
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while (GET_DMA_COUNT(count) > 0) \
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{ \
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if (count < 32) \
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count = 1; \
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else \
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count <<= 1; \
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while (--count > 0) NULL; \
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} \
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}
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#define WAIT_DMA_COMPLETE \
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{ \
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CHECK_ERROR(); \
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if (!(pThisDisplay->pGLInfo->GlintBoardStatus & GLINT_DMA_COMPLETE)) { \
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if (pThisDisplay->pGLInfo->GlintBoardStatus & GLINT_INTR_CONTEXT) { \
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static int retry = 0; \
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while (!(pThisDisplay->pGLInfo->GlintBoardStatus & GLINT_DMA_COMPLETE)) \
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{ \
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LOCKUP(); \
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} \
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} else { \
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if (pThisDisplay->pGLInfo->dwCurrentContext == CONTEXT_DISPLAY_HANDLE) {\
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Wait_2D_DMA_Complete(pThisDisplay); \
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} \
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else { \
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PATIENTLY_WAIT_DMA(); \
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pThisDisplay->pGLInfo->GlintBoardStatus |= GLINT_DMA_COMPLETE; \
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} \
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} \
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ASSERTDD( READ_GLINT_CTRL_REG(DMACount) == 0, "DMACount not zero after WAIT_DMA_COMPLETE" );\
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ASSERTDD((READ_GLINT_CTRL_REG(ByDMAControl) & 3 ) == 0, "Bypass DMA not complete after WAIT_DMA_COMPLETE" );\
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} \
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else { \
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ASSERTDD( READ_GLINT_CTRL_REG(DMACount) == 0, "DMACount not zero despite GLINT_DMA_COMPLETE" );\
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ASSERTDD((READ_GLINT_CTRL_REG(ByDMAControl) & 3 ) == 0, "Bypass DMA not complete despite GLINT_DMA_COMPLETE" );\
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} \
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CHECK_ERROR(); \
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}
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#endif // WNT_DDRAW
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#if WNT_DDRAW
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#define SYNC_WITH_GLINT \
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vNTSyncWith2DDriver(pThisDisplay->ppdev); \
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SET_MAX_ERROR_CHECK_FIFO_SPACE
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#else
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#define SYNC_WITH_GLINT \
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DISPDBG(( DBGLVL, "SYNC_WITH_GLINT" )); \
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WAIT_DMA_COMPLETE \
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while( pThisDisplay->pGlint->InFIFOSpace < 6 ) /* void */ ; \
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SET_ERROR_CHECK_FIFO_SPACES(6); \
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LOAD_GLINT_REG(FilterMode, 0x400); \
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LOAD_GLINT_REG(Sync, 0); \
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LOAD_GLINT_REG(FilterMode, 0x0); \
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do { \
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while (pThisDisplay->pGlint->OutFIFOWords == 0) /* void */ ; \
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} while (pThisDisplay->pGlint->GPFifo[0] != 0x188); \
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DISPDBG((DBGLVL,"Sync at line %d in %s", __LINE__, __FILE__)); \
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SET_MAX_ERROR_CHECK_FIFO_SPACE
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#endif // WNT_DDRAW
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//-----------------------------------------------------------------------------
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//
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// FIFO EXCLUSIVE definitions & macros
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//
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//-----------------------------------------------------------------------------
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#else //!WANT_DMA
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#define WAIT_FIFO(a) \
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do { \
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__WAIT_GLINT_FIFO_SPACE(a); \
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__SET_FIFO_ENTRIES_LEFT(a); \
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__RESET_FIFO_ERROR_CHECK; \
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} while(0)
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#define P3_ENSURE_DX_SPACE(entries) \
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{ \
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dmaPtr = (unsigned long *) (DWORD)pThisDisplay->pGlint->GPFifo; \
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P3_DMA_COMMIT_BUFFER(); \
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__SET_DMA_ENTRIES_LEFT(entries); \
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__RESET_FIFO_ERROR_CHECK; \
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}
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#define P3_DMA_FLUSH_BUFFER() \
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{ \
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dmaPtr = (unsigned long *) pThisDisplay->pGlint->GPFifo; \
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P3_DMA_COMMIT_BUFFER(); \
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}
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#define WAIT_DMA_COMPLETE
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#define SYNC_WITH_GLINT \
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vNTSyncWith2DDriver(pThisDisplay->ppdev); \
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SET_MAX_ERROR_CHECK_FIFO_SPACE
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#endif // !WANT_DMA
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//-----------------------------------------------------------------------------
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//
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// Win9x specific definitons & macros
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//
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//-----------------------------------------------------------------------------
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#if W95_DDRAW
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// wait for DMA to complete (DMACount becomes zero). So as not to kill the
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// PCI bus bandwidth for the DMA put in a backoff based on the amount of data
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// still left to DMA. Also set the timer going if at any time, the count we
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// read is the same as the previous count.
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//
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#if DBG
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#define LOCKUP() \
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if(( ++retry & 0xfffff ) == 0 ) \
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{ \
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DISPDBG(( WRNLVL, "Locked up in WAIT_DMA_COMPLETE" \
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" - %d retries", retry )); \
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}
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#else
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#define LOCKUP()
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#endif
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#endif // W95_DDRAW
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//-----------------------------------------------------------------------------
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//
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// Macros used to send data to the Permedia 3 hardware
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//
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//-----------------------------------------------------------------------------
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#define SEND_P3_DATA(tag,data) \
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{ \
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MEMORY_BARRIER(); \
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dmaPtr[0] = tag##_Tag; \
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MEMORY_BARRIER(); \
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dmaPtr[1] = data; \
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MEMORY_BARRIER(); \
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dmaPtr+=2; \
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CHECK_FIFO(2); \
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}
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#define SEND_P3_DATA_OFFSET(tag,data, i) \
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{ \
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MEMORY_BARRIER(); \
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dmaPtr[0] = (tag##_Tag + i); \
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MEMORY_BARRIER(); \
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dmaPtr[1] = data; \
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MEMORY_BARRIER(); \
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dmaPtr += 2; CHECK_FIFO(2); \
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}
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#define COPY_P3_DATA(tag,data) \
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{ \
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MEMORY_BARRIER(); \
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dmaPtr[0] = tag##_Tag; \
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MEMORY_BARRIER(); \
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dmaPtr[1] = *((unsigned long*) &(data)); \
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MEMORY_BARRIER(); \
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dmaPtr += 2; \
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CHECK_FIFO(2); \
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}
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#define COPY_P3_DATA_OFFSET(tag,data,i) \
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{ \
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MEMORY_BARRIER(); \
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dmaPtr[0] = tag##_Tag + i; \
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MEMORY_BARRIER(); \
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dmaPtr[1] = *((unsigned long*) &(data)); \
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MEMORY_BARRIER(); \
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dmaPtr += 2; \
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CHECK_FIFO(2); \
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}
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#define P3RX_HOLD_CMD(tag, count) \
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{ \
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MEMORY_BARRIER(); \
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dmaPtr[0] = ( tag##_Tag | ((count-1) << 16)); \
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dmaPtr++; \
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CHECK_FIFO(1); \
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}
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#define P3_DMA_GET_BUFFER_ENTRIES( fifo_count ) \
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{ \
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P3_DMA_GET_BUFFER(); \
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WAIT_FIFO( fifo_count ); \
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P3_ENSURE_DX_SPACE((fifo_count)); \
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}
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#define ADD_FUNNY_DWORD(a) \
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{ \
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MEMORY_BARRIER(); \
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*dmaPtr++ = a; \
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MEMORY_BARRIER(); \
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CHECK_FIFO(1); \
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}
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//-----------------------------------------------------------------------------
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//
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// Setup/Clear discconnect signals
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//
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// Setting the FIFODiscon register to 1 forces host write retries until
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// the data is accepted (might affect other time-critical processes though)
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//
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//-----------------------------------------------------------------------------
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#if DBG
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#define NO_FIFO_CHECK pThisDisplay->EntriesLeft = -20000;
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#define END_NO_FIFO_CHECK pThisDisplay->EntriesLeft = 0;
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#else
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#define NO_FIFO_CHECK
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#define END_NO_FIFO_CHECK
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#endif
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#define SET_DISCONNECT_CONTROL(val) \
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if(pThisDisplay->pGLInfo->InterfaceType == GLINT_NON_DMA) \
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{ \
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WAIT_FIFO(1); \
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if(pThisDisplay->pGLInfo->dwFlags & GMVF_DELTA) \
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{ \
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LOAD_GLINT_REG(DeltaDisconnectControl,val); \
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} \
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else \
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{ \
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LOAD_GLINT_REG(FIFODiscon,val); \
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} \
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}
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#define TURN_ON_DISCONNECT \
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SET_DISCONNECT_CONTROL(0x1) \
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NO_FIFO_CHECK
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#define TURN_OFF_DISCONNECT \
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SET_DISCONNECT_CONTROL(0x0) \
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END_NO_FIFO_CHECK
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#define SET_D3D_DISCONNECT_CONTROL(val) \
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if(pThisDisplay->pGLInfo->InterfaceType == GLINT_NON_DMA) \
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{ \
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WAIT_FIFO(1); \
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if(pThisDisplay->pGLInfo->dwFlags & GMVF_DELTA) \
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{ \
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LOAD_GLINT_REG(DeltaDisconnectControl,val); \
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} \
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else \
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{ \
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LOAD_GLINT_REG(FIFODiscon,val); \
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} \
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}
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#define TURN_ON_D3D_DISCONNECT \
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SET_D3D_DISCONNECT_CONTROL(0x1) \
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NO_FIFO_CHECK
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#define TURN_OFF_D3D_DISCONNECT \
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SET_D3D_DISCONNECT_CONTROL(0x0) \
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END_NO_FIFO_CHECK
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//-----------------------------------------------------------------------------
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//
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// Macros used to switch the chips hardware context between DDRAW/D3D ops
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//
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//-----------------------------------------------------------------------------
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#define DDRAW_OPERATION(pContext, pThisDisplay) \
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{ \
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ASSERTDD(pThisDisplay, "Error: pThisDisplay invalid in DDRAW_OPERATION!");\
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if (!IS_DXCONTEXT_CURRENT(pThisDisplay)) \
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{ \
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DXCONTEXT_IMMEDIATE(pThisDisplay); \
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if (pThisDisplay->b2D_FIFOS == TRUE) \
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{ \
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HWC_SwitchToFIFO(pThisDisplay, pThisDisplay->pGLInfo); \
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} \
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else \
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{ \
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HWC_SwitchToDMA(pThisDisplay, pThisDisplay->pGLInfo); \
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} \
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HWC_SwitchToDDRAW(pThisDisplay, TRUE); \
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pThisDisplay->pGLInfo->dwDirectXState = DIRECTX_LASTOP_2D; \
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} \
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else \
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{ \
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if (pThisDisplay->pGLInfo->dwDirectXState != DIRECTX_LASTOP_2D) \
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{ \
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if (pThisDisplay->b2D_FIFOS == TRUE) \
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{ \
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HWC_SwitchToFIFO(pThisDisplay, pThisDisplay->pGLInfo); \
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} \
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else \
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{ \
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HWC_SwitchToDMA(pThisDisplay, pThisDisplay->pGLInfo); \
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} \
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HWC_SwitchToDDRAW(pThisDisplay, FALSE); \
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pThisDisplay->pGLInfo->dwDirectXState = DIRECTX_LASTOP_2D; \
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} \
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} \
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}
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#define D3D_OPERATION(pContext, pThisDisplay) \
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{ \
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ASSERTDD(pThisDisplay, "Error: pThisDisplay invalid in D3D_OPERATION!"); \
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ASSERTDD(pContext, "Error: pContext invalid in D3D_OPERATION!"); \
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if (!IS_DXCONTEXT_CURRENT(pThisDisplay)) \
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{ \
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DXCONTEXT_IMMEDIATE(pThisDisplay); \
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if (pContext->b3D_FIFOS == TRUE) \
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{ \
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HWC_SwitchToFIFO(pThisDisplay, pThisDisplay->pGLInfo); \
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} \
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else \
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{ \
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HWC_SwitchToDMA(pThisDisplay, pThisDisplay->pGLInfo); \
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} \
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HWC_SwitchToD3D(pContext, pThisDisplay, TRUE); \
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pThisDisplay->pGLInfo->dwDirectXState = (ULONG_PTR)pContext; \
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} \
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else \
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{ \
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if ((pThisDisplay->pGLInfo->dwDirectXState != (ULONG_PTR)pContext) || \
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(pContext->dwDirtyFlags & CONTEXT_DIRTY_RENDER_OFFSETS)) \
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{ \
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if (pContext->b3D_FIFOS == TRUE) \
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{ \
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HWC_SwitchToFIFO(pThisDisplay, pThisDisplay->pGLInfo); \
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} \
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else \
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{ \
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HWC_SwitchToDMA(pThisDisplay, pThisDisplay->pGLInfo); \
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} \
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HWC_SwitchToD3D(pContext, pThisDisplay, FALSE); \
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pThisDisplay->pGLInfo->dwDirectXState = (ULONG_PTR)pContext; \
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} \
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} \
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}
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// Function to update the DDDRAW & D3D Software copy
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void HWC_SwitchToDDRAW( P3_THUNKEDDATA* pThisDisplay, BOOL bDXEntry );
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void HWC_SwitchToD3D(struct _p3_d3dcontext* pContext,
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struct tagThunkedData* pThisDisplay, BOOL bDXEntry);
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#endif __DMA_H
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