Leaked source code of windows server 2003
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  1. /***************************************************************************\
  2. *
  3. * ************************
  4. * * MINIPORT SAMPLE CODE *
  5. * ************************
  6. *
  7. * Module Name:
  8. *
  9. * interupt.h
  10. *
  11. * Abstract:
  12. *
  13. * This module contains the definitions for the shared memory used by
  14. * the interrupt control routines.
  15. *
  16. * Environment:
  17. *
  18. * Kernel mode
  19. *
  20. *
  21. * Copyright (c) 1994-1999 3Dlabs Inc. Ltd. All rights reserved.
  22. * Copyright (c) 1995-2003 Microsoft Corporation. All Rights Reserved.
  23. *
  24. \***************************************************************************/
  25. //
  26. // we manage a queue of DMA buffers that are to be loaded under interrupt control.
  27. // Each entry has a physical address and a count to be loaded into Permedia 3.
  28. // The command can be used to indicate other things to do in the DMA interrupt.
  29. //
  30. typedef struct _glint_dma_queue {
  31. ULONG command;
  32. ULONG address;
  33. ULONG count;
  34. } DMABufferQueue;
  35. typedef struct PXRXdmaInfo_Tag {
  36. volatile ULONG scheme; // Used by the interrupt handler only
  37. volatile ULONG hostInId; // Current internal HostIn id,
  38. // used by the HIid DMA scheme
  39. volatile ULONG fifoCount; // Current internal FIFO count,
  40. // used by various DMA schemes
  41. volatile ULONG NTbuff; // Current buffer number (0 or 1)
  42. volatile ULONG *NTptr; // 32/64 bit ptr
  43. // Last address written to by NT
  44. // (but not necesserily the end of
  45. // a completed buffer)
  46. volatile ULONG *NTdone; // 32/64 bit ptr
  47. // Last address NT has finished with
  48. // (end of a buffer, but not
  49. // necessarily sent to P3 yet)
  50. volatile ULONG *P3at; // 32/64 bit ptr
  51. // Last address sent to the P3
  52. volatile BOOLEAN bFlushRequired; // Is a flush required to empty
  53. // the FBwrite unit's cache?
  54. ULONG *DMAaddrL[2]; // 32/64 bit ptr
  55. // Linear address of the start
  56. // of each DMA buffer
  57. ULONG *DMAaddrEndL[2]; // 32/64 bit ptr
  58. // Linear address of the end of
  59. // each DMA buffer
  60. ULONG DMAaddrP[2]; // 32 bit ptr
  61. // Physical address of the start of
  62. // each DMA buffer
  63. ULONG DMAaddrEndP[2]; // 32 bit ptr
  64. // Physical address of the end of
  65. // each DMA buffer
  66. } PXRXdmaInfo;
  67. // interrupt status bits
  68. typedef enum {
  69. DMA_INTERRUPT_AVAILABLE = 0x01, // can use DMA interrupts
  70. VBLANK_INTERRUPT_AVAILABLE = 0x02, // can use VBLANK interrupts
  71. SUSPEND_DMA_TILL_VBLANK = 0x04, // Stop doing DMA till after next VBLANK
  72. DIRECTDRAW_VBLANK_ENABLED = 0x08, // Set flag for DirectDraw on VBLANK
  73. PXRX_SEND_ON_VBLANK_ENABLED = 0x10, // Set flag for PXRX DMA on VBLANK
  74. PXRX_CHECK_VFIFO_IN_VBLANK = 0x20, // Set flag for VFIFO underrun checking on VBLANK
  75. } INTERRUPT_CONTROL;
  76. // commands to the interrupt controller on the next VBLANK
  77. typedef enum {
  78. NO_COMMAND = 0,
  79. COLOR_SPACE_BUFFER_0,
  80. COLOR_SPACE_BUFFER_1,
  81. } VBLANK_CONTROL_COMMAND;
  82. // Display driver structure for 'general use'.
  83. typedef struct _pointer_interrupt_control
  84. {
  85. volatile ULONG bDisplayDriverHasAccess;
  86. volatile ULONG bMiniportHasAccess;
  87. volatile ULONG bInterruptPending;
  88. volatile ULONG bHidden;
  89. volatile ULONG CursorMode;
  90. volatile ULONG x, y;
  91. } PTR_INTR_CTL;
  92. // Display driver structure for 'pointer use'.
  93. typedef struct _general_interrupt_control
  94. {
  95. volatile ULONG bDisplayDriverHasAccess;
  96. volatile ULONG bMiniportHasAccess;
  97. } GEN_INTR_CTL;
  98. #define MAX_DMA_QUEUE_ENTRIES 10
  99. typedef struct _glint_interrupt_control {
  100. // contains various status bits. ** MUST BE THE FIRST FIELD **
  101. volatile INTERRUPT_CONTROL Control;
  102. // profiling counters for Permedia3 busy time
  103. ULONG PerfCounterShift;
  104. ULONG BusyTime; // at DMA interrupt add (TimeNow-StartTime) to this
  105. ULONG StartTime; // set this when DMACount is loaded
  106. ULONG IdleTime;
  107. ULONG IdleStart;
  108. // commands to perform on the next VBLANK
  109. volatile VBLANK_CONTROL_COMMAND VBCommand;
  110. // flag to indicate whether we expect another DMA interrupt
  111. volatile ULONG InterruptPending;
  112. volatile ULONG DDRAW_VBLANK; // flag for DirectDraw to indicate that a VBLANK occured.
  113. volatile ULONG bOverlayEnabled; // TRUE if the overlay is on at all
  114. volatile ULONG bVBLANKUpdateOverlay; // TRUE if the overlay needs to be updated by the VBLANK routine.
  115. volatile ULONG VBLANKUpdateOverlayWidth; // overlay width (updated in vblank)
  116. volatile ULONG VBLANKUpdateOverlayHeight; // overlay height (updated in vblank)
  117. // Volatile structures are required to enforce single-threading
  118. // We need 1 for general display use and 1 for pointer use, because
  119. // the pointer is synchronous.
  120. volatile PTR_INTR_CTL Pointer;
  121. volatile GEN_INTR_CTL General;
  122. // dummy DMA buffer to cause an interrupt but transfer no data
  123. ULONG dummyDMAAddress;
  124. ULONG dummyDMACount;
  125. // index offsets into the queue for the front, back and end. Using separate
  126. // front and back offsets allows the display driver to add and the interrupt
  127. // controller to remove entries without a need for locking code.
  128. volatile ULONG frontIndex;
  129. ULONG backIndex;
  130. ULONG endIndex;
  131. ULONG maximumIndex;
  132. // For P3RX 2D DMA:
  133. ULONG lastAddr;
  134. PXRXdmaInfo pxrxDMA;
  135. // array to contain the DMA queue
  136. DMABufferQueue dmaQueue[MAX_DMA_QUEUE_ENTRIES];
  137. } INTERRUPT_CONTROL_BLOCK, *PINTERRUPT_CONTROL_BLOCK;
  138. #define REQUEST_INTR_CMD_BLOCK_MUTEX(pBlock, bHaveMutex) \
  139. { \
  140. pBlock->bMiniportHasAccess = TRUE; \
  141. if(!pBlock->bDisplayDriverHasAccess) \
  142. { \
  143. bHaveMutex = TRUE; \
  144. } \
  145. else \
  146. { \
  147. bHaveMutex = FALSE; \
  148. pBlock->bMiniportHasAccess = FALSE; \
  149. } \
  150. }
  151. #define RELEASE_INTR_CMD_BLOCK_MUTEX(pBlock) \
  152. { \
  153. pBlock->bMiniportHasAccess = FALSE; \
  154. }
  155. //
  156. // structure containing information about the interrupt control block
  157. //
  158. typedef struct _interrupt_control_buffer_ {
  159. PHYSICAL_ADDRESS PhysAddress;
  160. INTERRUPT_CONTROL_BLOCK ControlBlock;
  161. PVOID kdpc;
  162. BOOLEAN bInterruptsInitialized;
  163. } PERM3_INTERRUPT_CTRLBUF, *PPERM3_INTERRUPT_CTRLBUF;