Leaked source code of windows server 2003
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229 lines
6.5 KiB

  1. /*++
  2. Copyright (c) 1992 Microsoft Corporation
  3. Module Name:
  4. ia64 psr
  5. Abstract:
  6. KD Extension Api
  7. Author:
  8. Thierry Fevrier (v-thief)
  9. Environment:
  10. User Mode.
  11. Revision History:
  12. --*/
  13. #include "precomp.h"
  14. #pragma hdrstop
  15. #include "psr.h"
  16. //
  17. // EmPsrFields: EM register fields for the Processor Status Register.
  18. //
  19. EM_REG_FIELD EmPsrFields[] = {
  20. { "rv", "reserved0" , 0x1, 0 }, // 0
  21. { "be", "Big-Endian" , 0x1, 1 }, // 1
  22. { "up", "User Performance monitor enable", 0x1, 2 }, // 2
  23. { "ac", "Alignment Check", 0x1, 3 }, // 3
  24. { "mfl", "Lower floating-point registers written", 0x1, 4 }, // 4
  25. { "mfh", "Upper floating-point registers written", 0x1, 5 }, // 5
  26. { "rv", "reserved1", 0x7, 6 }, // 6-12
  27. { "ic", "Interruption Collection", 0x1, 13 }, // 13
  28. { "i", "Interrupt enable", 0x1, 14 }, // 14
  29. { "pk", "Protection Key enable", 0x1, 15 }, // 15
  30. { "rv", "reserved2", 0x1, 16 }, // 16
  31. { "dt", "Data Address Translation enable", 0x1, 17 }, // 17
  32. { "dfl", "Disabled Floating-point Low register set", 0x1, 18 }, // 18
  33. { "dfh", "Disabled Floating-point High register set", 0x1, 19 }, // 19
  34. { "sp", "Secure Performance monitors", 0x1, 20 }, // 20
  35. { "pp", "Privileged Performance monitor enable", 0x1, 21 }, // 21
  36. { "di", "Disable Instruction set transition", 0x1, 22 }, // 22
  37. { "si", "Secure Interval timer", 0x1, 23 }, // 23
  38. { "db", "Debug Breakpoint fault enable", 0x1, 24 }, // 24
  39. { "lp", "Lower Privilege transfer trap enable", 0x1, 25 }, // 25
  40. { "tb", "Taken Branch trap enable", 0x1, 26 }, // 26
  41. { "rt", "Register stack translation enable", 0x1, 27 }, // 27
  42. { "rv", "reserved3", 0x4, 28 }, // 28-31
  43. { "cpl", "Current Privilege Level", 0x2, 32 }, // 32-33
  44. { "is", "Instruction Set", 0x1, 34 }, // 34
  45. { "mc", "Machine Abort Mask delivery disable", 0x1, 35 }, // 35
  46. { "it", "Instruction address Translation enable", 0x1, 36 }, // 36
  47. { "id", "Instruction Debug fault disable", 0x1, 37 }, // 37
  48. { "da", "Disable Data Access and Dirty-bit faults", 0x1, 38 }, // 38
  49. { "dd", "Data Debug fault disable", 0x1, 39 }, // 39
  50. { "ss", "Single Step enable", 0x1, 40 }, // 40
  51. { "ri", "Restart Instruction", 0x2, 41 }, // 41-42
  52. { "ed", "Exception Deferral", 0x1, 43 }, // 43
  53. { "bn", "register Bank", 0x1, 44 }, // 44
  54. { "ia", "Disable Instruction Access-bit faults", 0x1, 45 }, // 45
  55. { "rv", "reserved4", 0x12, 46 } // 46-63
  56. };
  57. VOID
  58. DisplayFullEmRegField(
  59. ULONG64 EmRegValue,
  60. EM_REG_FIELD EmRegFields[],
  61. ULONG Field
  62. )
  63. {
  64. dprintf( "\n %3.3s : %I64x : %-s",
  65. EmRegFields[Field].SubName,
  66. (EmRegValue >> EmRegFields[Field].Shift) & ((1 << EmRegFields[Field].Length) - 1),
  67. EmRegFields[Field].Name
  68. );
  69. return;
  70. } // DisplayFullEmRegField()
  71. VOID
  72. DisplayFullEmReg(
  73. IN ULONG64 Val,
  74. IN EM_REG_FIELD EmRegFields[],
  75. IN DISPLAY_MODE DisplayMode
  76. )
  77. {
  78. ULONG i, j;
  79. i = j = 0;
  80. if ( DisplayMode >= DISPLAY_MAX ) {
  81. while( j < EM_REG_BITS ) {
  82. DisplayFullEmRegField( Val, EmRegFields, i );
  83. j += EmRegFields[i].Length;
  84. i++;
  85. }
  86. }
  87. else {
  88. while( j < EM_REG_BITS ) {
  89. if ( !strstr(EmRegFields[i].Name, "reserved" ) &&
  90. !strstr(EmRegFields[i].Name, "ignored" ) ) {
  91. DisplayFullEmRegField( Val, EmRegFields, i );
  92. }
  93. j += EmRegFields[i].Length;
  94. i++;
  95. }
  96. }
  97. dprintf("\n");
  98. return;
  99. } // DisplayFullEmReg()
  100. VOID
  101. DisplayPsrIA64(
  102. IN const PCHAR Header,
  103. IN EM_PSR EmPsr,
  104. IN DISPLAY_MODE DisplayMode
  105. )
  106. {
  107. dprintf("%s", Header ? Header : "" );
  108. if ( DisplayMode >= DISPLAY_MED ) {
  109. DisplayFullEmReg( EM_PSRToULong64(EmPsr), EmPsrFields, DisplayMode );
  110. }
  111. else {
  112. dprintf(
  113. "ia bn ed ri ss dd da id it mc is cpl rt tb lp db\n\t\t "
  114. "%1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x\n\t\t"
  115. "si di pp sp dfh dfl dt pk i ic | mfh mfl ac up be\n\t\t "
  116. "%1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x | %1I64x %1I64x %1I64x %1I64x %1I64x\n",
  117. EmPsr.ia,
  118. EmPsr.bn,
  119. EmPsr.ed,
  120. EmPsr.ri,
  121. EmPsr.ss,
  122. EmPsr.dd,
  123. EmPsr.da,
  124. EmPsr.id,
  125. EmPsr.it,
  126. EmPsr.mc,
  127. EmPsr.is,
  128. EmPsr.cpl,
  129. EmPsr.rt,
  130. EmPsr.tb,
  131. EmPsr.lp,
  132. EmPsr.db,
  133. EmPsr.si,
  134. EmPsr.di,
  135. EmPsr.pp,
  136. EmPsr.sp,
  137. EmPsr.dfh,
  138. EmPsr.dfl,
  139. EmPsr.dt,
  140. EmPsr.pk,
  141. EmPsr.i,
  142. EmPsr.ic,
  143. EmPsr.mfh,
  144. EmPsr.mfl,
  145. EmPsr.ac,
  146. EmPsr.up,
  147. EmPsr.be
  148. );
  149. }
  150. return;
  151. } // DisplayPsrIA64()
  152. DECLARE_API( psr )
  153. /*++
  154. Routine Description:
  155. Dumps an IA64 Processor Status Word
  156. Arguments:
  157. args - Supplies the address in hex.
  158. Return Value:
  159. None
  160. --*/
  161. {
  162. ULONG64 psrValue;
  163. ULONG result;
  164. ULONG flags = 0;
  165. char *header;
  166. result = sscanf(args,"%X %lx", &psrValue, &flags);
  167. psrValue = GetExpression(args);
  168. if ((result != 1) && (result != 2)) {
  169. //
  170. // If user specified "@ipsr"...
  171. //
  172. char ipsrStr[16];
  173. result = sscanf(args, "%15s %lx", ipsrStr, &flags);
  174. if ( ((result != 1) && (result != 2)) || strcmp(ipsrStr,"@ipsr") ) {
  175. dprintf("USAGE: !psr 0xValue [display_mode:0,1,2]\n");
  176. dprintf("USAGE: !psr @ipsr [display_mode:0,1,2]\n");
  177. return E_INVALIDARG;
  178. }
  179. psrValue = GetExpression("@ipsr");
  180. }
  181. header = (flags > DISPLAY_MIN) ? NULL : "\tpsr:\t";
  182. if (TargetMachine != IMAGE_FILE_MACHINE_IA64)
  183. {
  184. dprintf("!psr not implemented for this architecture.\n");
  185. }
  186. else
  187. {
  188. DisplayPsrIA64( header, ULong64ToEM_PSR(psrValue), flags );
  189. }
  190. return S_OK;
  191. } // !psr