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1142 lines
40 KiB
1142 lines
40 KiB
/*++
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Copyright (c) 1992-2000 Microsoft Corporation
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Module Name:
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analysis.c
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Abstract:
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This module contains the main file of the analysis
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module.
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Author:
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Ori Gershony (t-orig) creation-date 6-July-1995
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Revision History:
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24-Aug-1999 [askhalid] copied from 32-bit wx86 directory and make work for 64bit.
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--*/
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#include <nt.h>
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#include <ntrtl.h>
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#include <nturtl.h>
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#include <windows.h>
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#include <wx86.h>
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#include <wx86nt.h>
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#include <wx86cpu.h>
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#include <cpuassrt.h>
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#include <threadst.h>
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#include <instr.h>
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#include <analysis.h>
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#include <decoder.h>
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#include <frag.h>
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#include <config.h>
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#include <compiler.h>
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ASSERTNAME;
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//
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// Macro to determine when to stop looking ahead during compilation.
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//
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#define STOP_DECODING(inst) (Fragments[inst.Operation].Flags & OPFL_STOP_COMPILE)
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//
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// Map a REG_ constant (offset into cpu struct) into register bit map
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// used by instruction data.
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//
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const DWORD MapRegNumToRegBits[0x1e] =
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{REGEAX, REGECX, REGEDX, REGEBX, REGESP, REGEBP, REGESI, REGEDI,
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0, 0, 0, 0, 0, 0,
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REGAX, REGCX, REGDX, REGBX, REGSP, REGBP, REGSI, REGDI,
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REGAL, REGCL, REGDL, REGBL, REGAH, REGCH, REGDH, REGBH };
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ULONG
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LocateEntryPoints(
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PINSTRUCTION InstructionStream,
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ULONG NumberOfInstructions
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)
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/*++
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Routine Description:
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This function scans the InstructionStream and marks instructions
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which begin entrypoint. An instruction begins an entrypoint if its
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EntryPoint field has a different value than the previous instruction's
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value. No instruction will have a NULL pointer.
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Note that in this pass, the EntryPoint field does *not* point to an
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ENTRYPOINT structure... it is only a marker.
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Arguments:
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IntelStart -- The intel address of the first instruction in the stream
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IntelStart -- The last byte of the last intel instruction in the stream
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Return Value:
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Count of EntryPoints located.
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--*/
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{
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ULONG i, j, intelDest;
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ULONG EntryPointCounter;
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ULONG IntelStart;
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ULONG IntelEnd;
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if (CompilerFlags & COMPFL_SLOW) {
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//
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// The compiler is supposed to generate slowmode code. Each
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// x86 instruction gets its own ENTRYPOINT
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//
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EntryPointCounter=1;
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for (i=0; i<NumberOfInstructions; i++) {
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//
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// Mark all instructions which don't correspond to 0-byte NOPs
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// following optimized instructions as starting EntryPoints.
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//
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if (InstructionStream[i].Size) {
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EntryPointCounter++;
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}
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InstructionStream[i].EntryPoint = (PENTRYPOINT)EntryPointCounter;
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}
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} else {
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//
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// Find all instructions which need Entrypoints.
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// Performance is O(n^2) in the worst case, although
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// it will be typically much closer to O(n)
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//
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// Instructions which mark the starts of Entrypoints have
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// their .EntryPoint pointer set to non-NULL. Instructions which
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// don't require entrypoints have it set to NULL;
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//
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IntelStart = InstructionStream[0].IntelAddress;
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IntelEnd = IntelStart +
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InstructionStream[NumberOfInstructions-1].IntelAddress +
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InstructionStream[NumberOfInstructions-1].Size;
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//
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// The first instruction always gets an entrypoint
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//
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InstructionStream[0].EntryPoint = (PENTRYPOINT)1;
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//
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// Visit each instruction in turn
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//
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for (i=0; i<NumberOfInstructions; i++) {
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if (((i+1) < NumberOfInstructions) &&
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(Fragments[InstructionStream[i].Operation].Flags & OPFL_END_NEXT_EP)) {
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//
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// This instruction marks the end of an Entrypoint. The next
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// instruction gets a new Entrypoint.
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//
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CPUASSERT(i < CpuInstructionLookahead-1 && i < NumberOfInstructions-1);
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InstructionStream[i+1].EntryPoint = (PENTRYPOINT)1;
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}
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// Now see if it is a direct control transfer instruction with a
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// destination that lies within this instruction stream. If it is,
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// we want to create an Entry Point at the destination so that the
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// control transfer will be compiled directly to the patched form,
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// and won't have to be patched later.
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//
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if (Fragments[InstructionStream[i].Operation].Flags & OPFL_CTRLTRNS) {
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//
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// The instruction is a direct control-transfer. If the
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// destination is within the InstructionStream, create an
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// Entrypoint at the destination.
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//
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if (InstructionStream[i].Operand1.Type == OPND_IMM ||
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InstructionStream[i].Operand1.Type == OPND_NOCODEGEN) {
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// Get the intel destination from the instruction structure.
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intelDest = InstructionStream[i].Operand1.Immed;
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} else {
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CPUASSERT(InstructionStream[i].Operand1.Type == OPND_ADDRREF );
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// A FAR instruction - Operand1 is a ptr to a SEL:OFFSET pair
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intelDest = *(UNALIGNED PULONG)(InstructionStream[i].Operand1.Immed);
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}
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// Get the intel destination from the instruction structure.
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// It is always an immediate with direct control transfers.
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if ((intelDest >= IntelStart) && (intelDest <= IntelEnd)) {
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//
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// Destination of the control-transfer is within the
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// instructionstream. Find the destination instruction.
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//
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if (intelDest > InstructionStream[i].IntelAddress) {
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//
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// The dest. address is at a higher address.
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//
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for (j=i+1; j<NumberOfInstructions; ++j) {
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if (InstructionStream[j].IntelAddress == intelDest) {
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break;
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}
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}
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} else {
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//
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// The dest. address is at a lower address.
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//
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for (j=i; j>0; --j) {
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if (InstructionStream[j].IntelAddress == intelDest) {
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break;
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}
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}
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}
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//
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// An exact match may not be found in the event that the
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// app is punning (either a real pun or the app is jumping
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// into the middle of an optimized instruction). In
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// either of the cases, defer entrypoint creation until
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// the branch is actually taken.
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//
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if (j >= 0 && j < NumberOfInstructions) {
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//
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// Exact match was found. Create an Entrypoint.
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//
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InstructionStream[j].EntryPoint = (PENTRYPOINT)1;
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}
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}
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} // if OPFL_CTRLTRNS
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} // for ()
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//
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// Convert the EntryPoint field from NULL/non-NULL to a unique
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// value for each range of instructions.
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//
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EntryPointCounter=1;
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i=0;
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while (i<NumberOfInstructions) {
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//
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// This instruction marks the beginning of a basic block
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//
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InstructionStream[i].EntryPoint = (PENTRYPOINT)EntryPointCounter;
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j=i+1;
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while (j < NumberOfInstructions) {
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if ((j >= NumberOfInstructions) ||
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(InstructionStream[j].Size && InstructionStream[j].EntryPoint)) {
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//
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// Either ran out of instructions, or encountered an instruction
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// which marks the start of the next basic block. Note that
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// 0-byte NOP instructions are not allowed to start basic blocks
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// as that violates the rules of OPT_ instructions.
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//
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break;
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}
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InstructionStream[j].EntryPoint = (PENTRYPOINT)EntryPointCounter;
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j++;
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}
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EntryPointCounter++;
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i = j;
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}
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} // if not COMPFL_SLOW
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//
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// At this point, EntryPointCounter holds the number of EntryPoints
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// plus one, because we started the counter at 1, not 0. Correct
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// that now.
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//
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EntryPointCounter--;
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return EntryPointCounter;
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}
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VOID
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UpdateRegs(
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PINSTRUCTION pInstr,
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POPERAND Operand
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)
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/*++
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Routine Description:
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Updates the list of registers referenced and/or modified based on the
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Operand.
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Arguments:
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pInstr -- the instruction to examine
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Operand -- the operand of the instruction to examine
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Return Value:
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return-value - none
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--*/
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{
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switch (Operand->Type) {
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case OPND_NOCODEGEN:
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case OPND_REGREF:
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if (Operand->Reg != NO_REG) {
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pInstr->RegsSet |= MapRegNumToRegBits[Operand->Reg];
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}
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break;
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case OPND_REGVALUE:
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if (Operand->Reg != NO_REG) {
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pInstr->RegsNeeded |= MapRegNumToRegBits[Operand->Reg];
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}
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break;
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case OPND_ADDRREF:
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case OPND_ADDRVALUE8:
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case OPND_ADDRVALUE16:
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case OPND_ADDRVALUE32:
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if (Operand->Reg != NO_REG) {
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pInstr->RegsNeeded |= MapRegNumToRegBits[Operand->Reg];
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}
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if (Operand->IndexReg != NO_REG) {
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pInstr->RegsNeeded |= MapRegNumToRegBits[Operand->IndexReg];
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}
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break;
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default:
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break;
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}
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}
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VOID
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CacheIntelRegs(
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PINSTRUCTION InstructionStream,
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ULONG numInstr)
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/*++
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Routine Description:
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This function deterimes what x86 registers, if any, can be cached in
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RISC preserved registers.
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Arguments:
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InstructionStream -- The instruction stream returned by the decoder
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numInstr -- The length of InstructionStream
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Return Value:
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return-value - none
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--*/
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{
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PINSTRUCTION pInstr;
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BYTE RegUsage[REGCOUNT];
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DWORD RegsToCache;
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int i;
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PENTRYPOINT PrevEntryPoint;
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//
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// Calculate the RegsSet and RegsNeeded for the bottommost instruction
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//
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pInstr = &InstructionStream[numInstr-1];
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pInstr->RegsSet = Fragments[pInstr->Operation].RegsSet;
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PrevEntryPoint = pInstr->EntryPoint;
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UpdateRegs(pInstr, &pInstr->Operand1);
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UpdateRegs(pInstr, &pInstr->Operand2);
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UpdateRegs(pInstr, &pInstr->Operand3);
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//
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// For each 32-bit register used as a parameter to this instruction,
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// set the usage count to 1.
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//
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for (i=0; i<REGCOUNT; ++i) {
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if (pInstr->RegsNeeded & (REGMASK<<(REGSHIFT*i))) {
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RegUsage[i] = 1;
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} else {
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RegUsage[i] = 0;
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}
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}
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//
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// Loop over instruction stream from bottom to top, starting at the
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// second-to-last instruction
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//
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for (pInstr--; pInstr >= InstructionStream; pInstr--) {
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//
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// Calculate the RegsSet and RegsNeeded values for this instruction
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//
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pInstr->RegsSet = Fragments[pInstr->Operation].RegsSet;
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UpdateRegs(pInstr, &pInstr->Operand1);
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UpdateRegs(pInstr, &pInstr->Operand2);
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UpdateRegs(pInstr, &pInstr->Operand3);
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RegsToCache = 0;
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if (PrevEntryPoint != pInstr->EntryPoint) {
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//
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// The current instruction marks the end of an Entrypoint.
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//
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PrevEntryPoint = pInstr->EntryPoint;
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//
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// For all x86 registers which have been read more than once
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// but not modified in the basic block, load them into the
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// cache before executing the first instruction in the basic
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// block.
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//
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for (i=0; i<REGCOUNT; ++i) {
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if (RegUsage[i] > 1) {
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RegsToCache |= (REGMASK<<(REGSHIFT*i));
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}
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}
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//
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// Reset the RegUsage[] array to indicate no registers are
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// cached.
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//
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RtlZeroMemory(RegUsage, REGCOUNT);
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} else {
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//
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// For each 32-bit x86 register modified by this instruction,
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// update the caching info.
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//
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for (i=0; i<REGCOUNT; ++i) {
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DWORD RegBits = pInstr->RegsSet & (REGMASK<<(REGSHIFT*i));
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if (RegBits) {
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//
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// The ith 32-bit x86 register has been modified by this
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// instruction
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//
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if (RegUsage[i] > 1) {
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//
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// There is more than one consumer of the modified
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// value so it is worth caching.
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//
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RegsToCache |= RegBits;
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}
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//
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// Since this x86 register was dirtied by this instruction,
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// it usage count must be reset to 0.
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//
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RegUsage[i] = 0;
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}
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}
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}
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//
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// Update the list of x86 registers which can be loaded into
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// cache registers before the next instruction executes.
|
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//
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pInstr[1].RegsToCache |= RegsToCache;
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//
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// For each 32-bit register used as a parameter to this instruction,
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// bump the usage count.
|
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//
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for (i=0; i<REGCOUNT; ++i) {
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if (pInstr->RegsNeeded & (REGMASK<<(REGSHIFT*i))) {
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RegUsage[i]++;
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}
|
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}
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}
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}
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VOID
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OptimizeInstructionStream(
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PINSTRUCTION IS,
|
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ULONG numInstr
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)
|
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/*++
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Routine Description:
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This function performs various optimization on the instruction stream
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retured by the decoder.
|
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|
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Arguments:
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IS -- The instruction stream returned by the decoder
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numInstr -- The length of IS
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Return Value:
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return-value - none
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--*/
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{
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ULONG i;
|
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|
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CPUASSERTMSG(numInstr, "Cannot optimize 0-length instruction stream");
|
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|
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//
|
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// Pass 1: Optimize x86 instruction stream, replacing single x86
|
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// instructions with special-case instructions, and replacing
|
|
// multiple x86 instructions with single special-case OPT_
|
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// instructions
|
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//
|
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for (i=0; i<numInstr; ++i) {
|
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|
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switch (IS[i].Operation) {
|
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case OP_Push32:
|
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if (i < numInstr-2
|
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&& IS[i].Operand1.Type == OPND_REGVALUE){
|
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|
|
if (IS[i].Operand1.Reg == GP_EBP) {
|
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// OP_OPT_SetupStack --
|
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// push ebp
|
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// mov ebp, esp
|
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// sub esp, x
|
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if ((IS[i+1].Operation == OP_Mov32) &&
|
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(IS[i+1].Operand1.Type == OPND_REGREF) &&
|
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(IS[i+1].Operand1.Reg == GP_EBP) &&
|
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(IS[i+1].Operand2.Type == OPND_REGVALUE) &&
|
|
(IS[i+1].Operand2.Reg == GP_ESP) &&
|
|
(IS[i+2].Operation == OP_Sub32) &&
|
|
(IS[i+2].Operand1.Type == OPND_REGREF) &&
|
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(IS[i+2].Operand1.Reg == GP_ESP) &&
|
|
(IS[i+2].Operand2.Type == OPND_IMM)){
|
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|
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IS[i].Operation = OP_OPT_SetupStack;
|
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IS[i].Operand1.Type = OPND_IMM;
|
|
IS[i].Operand1.Immed = IS[i+2].Operand2.Immed;
|
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IS[i].Size += IS[i+1].Size + IS[i+2].Size;
|
|
IS[i].Operand2.Type = OPND_NONE;
|
|
IS[i+1].Operation = OP_Nop;
|
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IS[i+1].Operand1.Type = OPND_NONE;
|
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IS[i+1].Operand2.Type = OPND_NONE;
|
|
IS[i+1].Size = 0;
|
|
IS[i+2].Operation = OP_Nop;
|
|
IS[i+2].Operand1.Type = OPND_NONE;
|
|
IS[i+2].Operand2.Type = OPND_NONE;
|
|
IS[i+2].Size = 0;
|
|
i+=2;
|
|
break;
|
|
}
|
|
} else if (IS[i].Operand1.Reg == GP_EBX) {
|
|
// OP_OPT_PushEbxEsiEdi --
|
|
// push ebx
|
|
// push esi
|
|
// push edi
|
|
if ((IS[i+1].Operation == OP_Push32) &&
|
|
(IS[i+1].Operand1.Type == OPND_REGVALUE) &&
|
|
(IS[i+1].Operand1.Reg == GP_ESI) &&
|
|
(IS[i+2].Operation == OP_Push32) &&
|
|
(IS[i+2].Operand1.Type == OPND_REGVALUE) &&
|
|
(IS[i+2].Operand1.Reg == GP_EDI)){
|
|
|
|
IS[i].Operation = OP_OPT_PushEbxEsiEdi;
|
|
IS[i].Size += IS[i+1].Size + IS[i+2].Size;
|
|
IS[i].Operand1.Type = OPND_NONE;
|
|
IS[i].Operand2.Type = OPND_NONE;
|
|
IS[i+1].Operation = OP_Nop;
|
|
IS[i+1].Operand1.Type = OPND_NONE;
|
|
IS[i+1].Operand2.Type = OPND_NONE;
|
|
IS[i+1].Size = 0;
|
|
IS[i+2].Operation = OP_Nop;
|
|
IS[i+2].Operand1.Type = OPND_NONE;
|
|
IS[i+2].Operand2.Type = OPND_NONE;
|
|
IS[i+2].Size = 0;
|
|
i+=2;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
//
|
|
// It is not one of the other special PUSH sequences, so see
|
|
// if there are two consecutive PUSHes to merge together. Note:
|
|
// If the second PUSH references ESP, the two cannot be merged
|
|
// because the value is computed before 4 is subtracted from ESP.
|
|
// ie. the following is disallowed:
|
|
// PUSH EAX
|
|
// PUSH ESP ; second operand to Push2 would have been
|
|
// ; built before the PUSH EAX was executed.
|
|
//
|
|
if (i < numInstr-1 &&
|
|
!IS[i].FsOverride &&
|
|
!IS[i+1].FsOverride &&
|
|
IS[i+1].Operation == OP_Push32 &&
|
|
IS[i+1].Operand1.Reg != GP_ESP &&
|
|
IS[i+1].Operand1.IndexReg != GP_ESP) {
|
|
|
|
IS[i].Operation = OP_OPT_Push232;
|
|
IS[i].Operand2 = IS[i+1].Operand1;
|
|
IS[i].Size += IS[i+1].Size;
|
|
IS[i+1].Operation = OP_Nop;
|
|
IS[i+1].Operand1.Type = OPND_NONE;
|
|
IS[i+1].Size = 0;
|
|
i++;
|
|
}
|
|
|
|
break;
|
|
|
|
case OP_Pop32:
|
|
// OP_OPT_PopEdiEsiEbx
|
|
// pop edi
|
|
// pop esi
|
|
// pop ebx
|
|
if (i < numInstr-2 &&
|
|
(IS[i].Operand1.Type == OPND_REGREF) &&
|
|
(IS[i].Operand1.Reg == GP_EDI) &&
|
|
(IS[i+1].Operation == OP_Pop32) &&
|
|
(IS[i+1].Operand1.Type == OPND_REGREF) &&
|
|
(IS[i+1].Operand1.Reg == GP_ESI) &&
|
|
(IS[i+2].Operation == OP_Pop32) &&
|
|
(IS[i+2].Operand1.Type == OPND_REGREF) &&
|
|
(IS[i+2].Operand1.Reg == GP_EBX)){
|
|
|
|
IS[i].Operation = OP_OPT_PopEdiEsiEbx;
|
|
IS[i].Size += IS[i+1].Size + IS[i+2].Size;
|
|
IS[i].Operand1.Type = OPND_NONE;
|
|
IS[i].Operand2.Type = OPND_NONE;
|
|
IS[i+1].Operation = OP_Nop;
|
|
IS[i+1].Operand1.Type = OPND_NONE;
|
|
IS[i+1].Operand2.Type = OPND_NONE;
|
|
IS[i+1].Size = 0;
|
|
IS[i+2].Operation = OP_Nop;
|
|
IS[i+2].Operand1.Type = OPND_NONE;
|
|
IS[i+2].Operand2.Type = OPND_NONE;
|
|
IS[i+2].Size = 0;
|
|
i+=2;
|
|
} else if (i < numInstr-1 &&
|
|
!IS[i].FsOverride &&
|
|
!IS[i].FsOverride &&
|
|
IS[i].Operand1.Type == OPND_REGREF &&
|
|
IS[i+1].Operation == OP_Pop32 &&
|
|
IS[i+1].Operand1.Type == OPND_REGREF) {
|
|
|
|
// Fold the two POPs together. Both operands are REGREF,
|
|
// so there is no problem with interdependencies between
|
|
// memory touched by the first POP modifying the address
|
|
// of the second POP. ie. the following is not merged:
|
|
// POP EAX
|
|
// POP [EAX] ; depends on results of first POP
|
|
IS[i].Operation = OP_OPT_Pop232;
|
|
IS[i].Operand2 = IS[i+1].Operand1;
|
|
IS[i].Size += IS[i+1].Size;
|
|
IS[i+1].Operation = OP_Nop;
|
|
IS[i+1].Operand1.Type = OPND_NONE;
|
|
IS[i+1].Size = 0;
|
|
i++;
|
|
}
|
|
break;
|
|
|
|
case OP_Xor32:
|
|
case OP_Sub32:
|
|
if (IS[i].Operand1.Type == OPND_REGREF &&
|
|
IS[i].Operand2.Type == OPND_REGVALUE &&
|
|
IS[i].Operand1.Reg == IS[i].Operand2.Reg) {
|
|
// Instruction is XOR samereg, samereg (ie. XOR EAX, EAX),
|
|
// or SUB samereg, samereg (ie. SUB ECX, ECX).
|
|
// Emit OP_OPT_ZERO32 samereg
|
|
IS[i].Operand2.Type = OPND_NONE;
|
|
IS[i].Operation = OP_OPT_ZERO32;
|
|
}
|
|
break;
|
|
|
|
case OP_Test8:
|
|
if (IS[i].Operand1.Type == OPND_REGVALUE &&
|
|
IS[i].Operand2.Type == OPND_REGVALUE &&
|
|
IS[i].Operand1.Reg == IS[i].Operand2.Reg) {
|
|
// Instruction is TEST samereg, samereg (ie. TEST EAX, EAX)
|
|
// Emit OP_OPT_FastTest8/16/32
|
|
IS[i].Operand1.Type = OPND_REGVALUE;
|
|
IS[i].Operand2.Type = OPND_NONE;
|
|
IS[i].Operation = OP_OPT_FastTest8;
|
|
}
|
|
break;
|
|
|
|
case OP_Test16:
|
|
if (IS[i].Operand1.Type == OPND_REGVALUE &&
|
|
IS[i].Operand2.Type == OPND_REGVALUE &&
|
|
IS[i].Operand1.Reg == IS[i].Operand2.Reg) {
|
|
// Instruction is TEST samereg, samereg (ie. TEST EAX, EAX)
|
|
// Emit OP_OPT_FastTest8/16/32
|
|
IS[i].Operand1.Type = OPND_REGVALUE;
|
|
IS[i].Operand2.Type = OPND_NONE;
|
|
IS[i].Operation = OP_OPT_FastTest16;
|
|
}
|
|
break;
|
|
|
|
case OP_Test32:
|
|
if (IS[i].Operand1.Type == OPND_REGVALUE &&
|
|
IS[i].Operand2.Type == OPND_REGVALUE &&
|
|
IS[i].Operand1.Reg == IS[i].Operand2.Reg) {
|
|
// Instruction is TEST samereg, samereg (ie. TEST EAX, EAX)
|
|
// Emit OP_OPT_FastTest8/16/32
|
|
IS[i].Operand1.Type = OPND_REGVALUE;
|
|
IS[i].Operand2.Type = OPND_NONE;
|
|
IS[i].Operation = OP_OPT_FastTest32;
|
|
}
|
|
break;
|
|
|
|
case OP_Cmp32:
|
|
if (i<numInstr+1 && IS[i+1].Operation == OP_Sbb32 &&
|
|
IS[i+1].Operand1.Type == OPND_REGREF &&
|
|
IS[i+1].Operand2.Type == OPND_REGVALUE &&
|
|
IS[i+1].Operand1.Reg == IS[i+1].Operand2.Reg) {
|
|
// The two instructions are:
|
|
// CMP anything1, anything2
|
|
// SBB samereg, samereg
|
|
// The optimized instruction is:
|
|
// Operation = either CmpSbb32 or CmpSbbNeg32
|
|
// Operand1 = &samereg (passed as REGREF)
|
|
// Operand2 = anything1 (passed as ADDRVAL32 or REGVAL)
|
|
// Operand3 = anything2 (passed as ADDRVAL32 or REGVAL)
|
|
IS[i].Operand3 = IS[i].Operand2;
|
|
IS[i].Operand2 = IS[i].Operand1;
|
|
IS[i].Operand1 = IS[i+1].Operand1;
|
|
if (i<numInstr+2 && IS[i+2].Operation == OP_Neg32 &&
|
|
IS[i+2].Operand1.Type == OPND_REGREF &&
|
|
IS[i+2].Operand1.Reg == IS[i+1].Operand1.Reg) {
|
|
// The third instruction is NEG samereg, samereg
|
|
IS[i].Operation = OP_OPT_CmpSbbNeg32;
|
|
IS[i+2].Operation = OP_Nop;
|
|
IS[i+2].Operand1.Type = OPND_NONE;
|
|
IS[i+2].Operand2.Type = OPND_NONE;
|
|
IS[i+2].Size = 0;
|
|
} else {
|
|
IS[i].Operation = OP_OPT_CmpSbb32;
|
|
}
|
|
IS[i+1].Operation = OP_Nop;
|
|
IS[i+1].Operand1.Type = OPND_NONE;
|
|
IS[i+1].Operand2.Type = OPND_NONE;
|
|
IS[i+1].Size = 0;
|
|
i++;
|
|
}
|
|
break;
|
|
|
|
case OP_Cwd16:
|
|
if (i<numInstr+1 && IS[i+1].Operation == OP_Idiv16) {
|
|
IS[i].Operation = OP_OPT_CwdIdiv16;
|
|
IS[i].Operand1 = IS[i+1].Operand1;
|
|
IS[i].Size += IS[i+1].Size;
|
|
IS[i+1].Operation = OP_Nop;
|
|
IS[i+1].Operand1.Type = OPND_NONE;
|
|
IS[i+1].Size = 0;
|
|
i++;
|
|
}
|
|
break;
|
|
|
|
case OP_Cwd32:
|
|
if (i<numInstr+1 && IS[i+1].Operation == OP_Idiv32) {
|
|
IS[i].Operation = OP_OPT_CwdIdiv32;
|
|
IS[i].Operand1 = IS[i+1].Operand1;
|
|
IS[i].Size += IS[i+1].Size;
|
|
IS[i+1].Operation = OP_Nop;
|
|
IS[i+1].Operand1.Type = OPND_NONE;
|
|
IS[i+1].Size = 0;
|
|
i++;
|
|
}
|
|
break;
|
|
|
|
case OP_FP_FNSTSW:
|
|
if (i<numInstr+1 && IS[i+1].Operation == OP_Sahf &&
|
|
IS[i].Operand1.Type == OPND_REGREF &&
|
|
IS[i].Operand1.Reg == GP_AX) {
|
|
|
|
// Replace FNSTSW AX / SAHF by one instruction
|
|
IS[i].Operation = OP_OPT_FNSTSWAxSahf;
|
|
IS[i].Operand1.Type = OPND_NONE;
|
|
IS[i].Size += IS[i+1].Size;
|
|
IS[i+1].Operation = OP_Nop;
|
|
IS[i+1].Size = 0;
|
|
i++;
|
|
}
|
|
break;
|
|
|
|
case OP_FP_FSTP_STi:
|
|
if (IS[i].Operand1.Immed == 0) {
|
|
IS[i].Operand1.Type = OPND_NONE;
|
|
IS[i].Operation = OP_OPT_FSTP_ST0;
|
|
}
|
|
break;
|
|
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
VOID
|
|
OptimizeIntelFlags(
|
|
PINSTRUCTION IS,
|
|
ULONG numInstr
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function analysis x86 flag register usage and switches instructions
|
|
to use NoFlags versions if possible.
|
|
|
|
Arguments:
|
|
|
|
IS -- The instruction stream returned by the decoder
|
|
|
|
numInstr -- The length of IS
|
|
|
|
Return Value:
|
|
|
|
return-value - none
|
|
|
|
--*/
|
|
{
|
|
USHORT FlagsNeeded; // flags required to execute current x86 instr
|
|
USHORT FlagsToGenerate; // flags which current x86 instr must generate
|
|
PFRAGDESCR pFragDesc; // ptr to Fragments[] array for current instr
|
|
ULONG i; // instruction index
|
|
BOOL fPassNeeded = TRUE;// TRUE if the outer loop needs to loop once more
|
|
ULONG PassNumber = 0; // number of times outer loop has looped
|
|
PENTRYPOINT pEPDest; // Entrypoint for destination of a ctrl transfer
|
|
USHORT KnownFlagsNeeded[MAX_INSTR_COUNT]; // flags needed for each instr
|
|
|
|
while (fPassNeeded) {
|
|
|
|
//
|
|
// This loop is executed at most two times. The second pass is only
|
|
// required if there is a control-transfer instruction whose
|
|
// destination is within the Instruction Stream and at a lower
|
|
// Intel address (ie. a backwards JMP).
|
|
//
|
|
fPassNeeded = FALSE;
|
|
PassNumber++;
|
|
CPUASSERT(PassNumber <= 2);
|
|
|
|
//
|
|
// Iterate over all x86 instructions decoded, from bottom to top,
|
|
// propagating flags info up. Start off by assuming all x86 flags
|
|
// must be up-to-date at the end of the last basic block.
|
|
//
|
|
FlagsNeeded = ALLFLAGS;
|
|
i = numInstr;
|
|
do {
|
|
i--;
|
|
pFragDesc = &Fragments[IS[i].Operation];
|
|
|
|
//
|
|
// Calculate what flags will need to be computed by this
|
|
// instruction and ones before this.
|
|
//
|
|
KnownFlagsNeeded[i] = FlagsNeeded | pFragDesc->FlagsNeeded;
|
|
FlagsToGenerate = FlagsNeeded & pFragDesc->FlagsSet;
|
|
|
|
//
|
|
// Calculate what flags this instruction will need to have
|
|
// computed before it can be executed.
|
|
//
|
|
FlagsNeeded = (FlagsNeeded & ~FlagsToGenerate) |
|
|
pFragDesc->FlagsNeeded;
|
|
|
|
if (pFragDesc->Flags & OPFL_CTRLTRNS) {
|
|
ULONG IntelDest = IS[i].Operand1.Immed;
|
|
|
|
//
|
|
// For control-transfer instructions, FlagsNeeded also includes
|
|
// the flags required for the destination of the transfer.
|
|
//
|
|
if (IS[0].IntelAddress <= IntelDest &&
|
|
i > 0 && IS[i-1].IntelAddress >= IntelDest) {
|
|
//
|
|
// The destination of the control-transfer is at a lower
|
|
// address in the Instruction Stream.
|
|
//
|
|
|
|
if (PassNumber == 1) {
|
|
//
|
|
// Need to make a second pass over the flags
|
|
// optimizations in order to determine what flags are
|
|
// needed for the destination address.
|
|
//
|
|
fPassNeeded = TRUE;
|
|
FlagsNeeded = ALLFLAGS; // assume all flags are needed
|
|
} else {
|
|
ULONG j;
|
|
USHORT NewFlagsNeeded;
|
|
|
|
//
|
|
// Search for the IntelDest within the Instruction
|
|
// Stream. IntelDest may not be found if there is
|
|
// a pun.
|
|
//
|
|
NewFlagsNeeded = ALLFLAGS; // assume there is a pun
|
|
for (j=0; j < i; ++j) {
|
|
if (IS[j].IntelAddress == IntelDest) {
|
|
NewFlagsNeeded = KnownFlagsNeeded[j];
|
|
break;
|
|
}
|
|
}
|
|
|
|
FlagsNeeded |= NewFlagsNeeded;
|
|
}
|
|
} else if (IS[i+1].IntelAddress <= IntelDest &&
|
|
IntelDest <= IS[numInstr-1].IntelAddress) {
|
|
//
|
|
// The destination of the control-transfer is at a higher
|
|
// address in the Instruction Stream. Pick up the
|
|
// already-computed FlagsNeeded for the destination.
|
|
//
|
|
ULONG j;
|
|
USHORT NewFlagsNeeded = ALLFLAGS; // assume a pun
|
|
|
|
for (j=i+1; j < numInstr; ++j) {
|
|
if (IS[j].IntelAddress == IntelDest) {
|
|
NewFlagsNeeded = KnownFlagsNeeded[j];
|
|
break;
|
|
}
|
|
}
|
|
|
|
FlagsNeeded |= NewFlagsNeeded;
|
|
|
|
} else {
|
|
//
|
|
// Destination of the control-transfer is unknown. Assume
|
|
// the worst: all flags are required.
|
|
//
|
|
FlagsNeeded = ALLFLAGS;
|
|
}
|
|
}
|
|
|
|
if (!(FlagsToGenerate & pFragDesc->FlagsSet) &&
|
|
(pFragDesc->Flags & OPFL_HASNOFLAGS)) {
|
|
//
|
|
// This instruction is not required to generate any flags, and
|
|
// it has a NOFLAGS version. Update the flags that need to be
|
|
// computed by instructions before this one, and modify the
|
|
// Operation number to point at the NoFlags fragment.
|
|
//
|
|
FlagsToGenerate &= pFragDesc->FlagsSet;
|
|
if (pFragDesc->Flags & OPFL_ALIGN) {
|
|
IS[i].Operation += 2;
|
|
} else {
|
|
IS[i].Operation ++;
|
|
}
|
|
|
|
if (IS[i].Operation == OP_OPT_ZERONoFlags32) {
|
|
//
|
|
// Special-case this to be a "mov [value], zero" so it is
|
|
// inlined.
|
|
//
|
|
IS[i].Operation = OP_Mov32;
|
|
IS[i].Operand2.Type = OPND_IMM;
|
|
IS[i].Operand2.Immed = 0;
|
|
}
|
|
}
|
|
} while (i);
|
|
}
|
|
}
|
|
|
|
VOID
|
|
DetermineEbpAlignment(
|
|
PINSTRUCTION InstructionStream,
|
|
ULONG numInstr
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
For each instruction in InstructionStream[], sets Instruction->EbpAligned
|
|
based on whether EBP is assumed to be DWORD-aligned or not. EBP is
|
|
assumed to be DWORD-aligned if a "MOV EBP, ESP" instruction is seen, and
|
|
it is assumed to become unaligned at the first instruction which is
|
|
flagged as modifying EBP.
|
|
|
|
Arguments:
|
|
|
|
InstructionStream -- The instruction stream returned by the decoder
|
|
|
|
numInstr -- The length of InstructionStream
|
|
|
|
Return Value:
|
|
|
|
return-value - none
|
|
|
|
--*/
|
|
{
|
|
ULONG i;
|
|
BOOL EbpAligned = FALSE;
|
|
|
|
for (i=0; i<numInstr; ++i) {
|
|
if (InstructionStream[i].RegsSet & REGEBP) {
|
|
//
|
|
// This instruction modified EBP
|
|
//
|
|
if (InstructionStream[i].Operation == OP_OPT_SetupStack ||
|
|
InstructionStream[i].Operation == OP_OPT_SetupStackNoFlags ||
|
|
(InstructionStream[i].Operation == OP_Mov32 &&
|
|
InstructionStream[i].Operand2.Type == OPND_REGVALUE &&
|
|
InstructionStream[i].Operand2.Reg == GP_ESP)) {
|
|
//
|
|
// The instruction is either "MOV EBP, ESP" or one of the
|
|
// SetupStack fragments (which contains a "MOV EBP, ESP")
|
|
// assume Ebp is aligned from now on.
|
|
//
|
|
EbpAligned = TRUE;
|
|
} else {
|
|
EbpAligned = FALSE;
|
|
}
|
|
}
|
|
|
|
InstructionStream[i].EbpAligned = EbpAligned;
|
|
}
|
|
}
|
|
|
|
ULONG
|
|
GetInstructionStream(
|
|
PINSTRUCTION InstructionStream,
|
|
PULONG NumberOfInstructions,
|
|
PVOID pIntelInstruction,
|
|
PVOID pLastIntelInstruction
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Returns an instruction stream to the compiler. The instruction
|
|
stream is terminated either when the buffer is full, or when
|
|
we reach a control transfer instruction.
|
|
|
|
Arguments:
|
|
|
|
InstructionStream -- A pointer to the buffer where the decoded
|
|
instructions are stored.
|
|
|
|
NumberOfInstructions -- Upon entry, this variable contains the
|
|
maximal number of instructions the buffer can hold. When
|
|
returning, it contains the actual number of instructions
|
|
decoded.
|
|
|
|
pIntelInstruction -- A pointer to the first real intel instruction
|
|
to be decoded.
|
|
|
|
pLastIntelInstruction -- A pointer to the last intel instruction to be
|
|
compiled, 0xffffffff if not used.
|
|
|
|
Return Value:
|
|
|
|
Number of entrypoints required to describe the decoded instruction
|
|
stream.
|
|
|
|
--*/
|
|
{
|
|
ULONG numInstr=0;
|
|
ULONG maxBufferSize;
|
|
ULONG cEntryPoints;
|
|
|
|
maxBufferSize = (*NumberOfInstructions);
|
|
|
|
//
|
|
// Zero-fill the InstructionStream. The decoder depends on this.
|
|
//
|
|
RtlZeroMemory(InstructionStream, maxBufferSize*sizeof(INSTRUCTION));
|
|
|
|
#if DBG
|
|
//
|
|
// Do a little analysis on the address we're about to decode. If
|
|
// the address is part of a non-x86 image, log that to the debugger.
|
|
// That probably indicates a thunking problem. If the address is not
|
|
// part of an image, warn that the app is running generated code.
|
|
//
|
|
try {
|
|
USHORT Instr;
|
|
|
|
//
|
|
// Try to read the instruction about to be executed. If we get
|
|
// an access violation, use 0 as the value of the instruction.
|
|
//
|
|
Instr = 0;
|
|
|
|
//
|
|
// Ignore BOP instructions - we assume we know what's going on with
|
|
// them.
|
|
//
|
|
if (Instr != 0xc4c4) {
|
|
|
|
NTSTATUS st;
|
|
MEMORY_BASIC_INFORMATION mbi;
|
|
|
|
st = NtQueryVirtualMemory(NtCurrentProcess(),
|
|
pIntelInstruction,
|
|
MemoryBasicInformation,
|
|
&mbi,
|
|
sizeof(mbi),
|
|
NULL);
|
|
if (NT_SUCCESS(st)) {
|
|
PIMAGE_NT_HEADERS Headers;
|
|
|
|
Headers = RtlImageNtHeader(mbi.AllocationBase);
|
|
if (!Headers || Headers->FileHeader.Machine != IMAGE_FILE_MACHINE_I386) {
|
|
LOGPRINT((TRACELOG, "CPU Analysis warning: jumping from Intel to non-intel code at 0x%X\r\n", pIntelInstruction));
|
|
}
|
|
} else {
|
|
// Eip isn't pointing anywhere???
|
|
}
|
|
}
|
|
} except(EXCEPTION_EXECUTE_HANDLER) {
|
|
;
|
|
}
|
|
#endif //DBG
|
|
|
|
while (numInstr < maxBufferSize) {
|
|
|
|
DecodeInstruction ((DWORD) (ULONGLONG)pIntelInstruction, InstructionStream+numInstr);
|
|
if ((STOP_DECODING(InstructionStream[numInstr])) ||
|
|
(pIntelInstruction >= pLastIntelInstruction)) {
|
|
|
|
// We reached a control transfer instruction
|
|
numInstr++;
|
|
(*NumberOfInstructions) = numInstr;
|
|
break; // SUCCESS
|
|
}
|
|
pIntelInstruction = (PVOID) ((ULONGLONG)pIntelInstruction + (InstructionStream+numInstr)->Size);
|
|
|
|
numInstr++;
|
|
}
|
|
|
|
//
|
|
// Optimize x86 code by merging x86 instructions into meta-instructions
|
|
// and cleaning up special x86 idioms.
|
|
//
|
|
if (!(CompilerFlags & COMPFL_SLOW)) {
|
|
OptimizeInstructionStream (InstructionStream, numInstr);
|
|
}
|
|
|
|
//
|
|
// Determine where all basic blocks are by filling in the EntryPoint
|
|
// field in each instruction. This must be done after
|
|
// OptimizeInstructionStream() runs so that EntryPoints don't fall
|
|
// into the middle of meta-instructions.
|
|
//
|
|
cEntryPoints = LocateEntryPoints(InstructionStream, numInstr);
|
|
|
|
//
|
|
// Perform optimizations which require knowledge of EntryPoints
|
|
//
|
|
if (numInstr > 2 && !(CompilerFlags & COMPFL_SLOW)) {
|
|
if (!CpuDisableNoFlags) {
|
|
OptimizeIntelFlags(InstructionStream, numInstr);
|
|
}
|
|
|
|
if (!CpuDisableRegCache) {
|
|
CacheIntelRegs(InstructionStream, numInstr);
|
|
}
|
|
|
|
if (!CpuDisableEbpAlign) {
|
|
DetermineEbpAlignment(InstructionStream, numInstr);
|
|
}
|
|
}
|
|
|
|
return cEntryPoints;
|
|
}
|