Source code of Windows XP (NT5)
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  1. /*++
  2. Copyright (c) 1993 Weitek Corporation
  3. Module Name:
  4. pci.h
  5. Abstract:
  6. This module contains PCI definitions for the Weitek P9 miniport
  7. device driver.
  8. Environment:
  9. Kernel mode
  10. Revision History may be found at the end of this file.
  11. --*/
  12. //
  13. // Local function prototypes defined in PCI.C.
  14. //
  15. BOOLEAN
  16. PciFindDevice(
  17. IN PHW_DEVICE_EXTENSION HwDeviceExtension,
  18. IN USHORT usDeviceId,
  19. IN USHORT usVendorId,
  20. IN OUT PULONG pulSlotNum
  21. );
  22. //
  23. // Externals used by the PCI routines.
  24. //
  25. extern VIDEO_ACCESS_RANGE VLDefDACRegRange[];
  26. #if 0
  27. //
  28. // Define P9 register/frame buffer addresses using the OEM's default
  29. // base address.
  30. //
  31. #define MemBase 0xA0000000
  32. #endif
  33. //
  34. // Bit to write to the sequencer control register to enable/disable P9
  35. // video output.
  36. //
  37. #define P9_VIDEO_ENB 0x10
  38. #define P9_VIDEO_DIS ~P9_VIDEO_ENB
  39. //
  40. // Define the bit in the sequencer control register which determines
  41. // the sync polarities. For Weitek board, 1 = positive.
  42. //
  43. #define HSYNC_POL_MASK 0x20
  44. #define POL_MASK HSYNC_POL_MASK
  45. #define VIPER_HSYNC_POL_MASK 0x40
  46. #define VIPER_VSYNC_POL_MASK 0x80
  47. //
  48. // Defines which are specific to the Weitek PCI Implementation.
  49. //
  50. #define WTK_VENDOR_ID (USHORT) 0x100E
  51. #define WTK_9001_ID (USHORT) 0x9001
  52. #define WTK_9002_ID (USHORT) 0x9002
  53. #define P9001_IO_RANGE 0x1000 // 4K worth of IO ports.
  54. #define WTK_9100_ID (USHORT) 0x9100
  55. //
  56. // Weitek P9001 specific configuration space registers.
  57. //
  58. #define P9001_CMD_REG 0x04
  59. #define P9001_REV_ID 0x08
  60. #define P9001_BASE_ADDR 0x10
  61. #define P9001_REG_BASE 0x14
  62. #define P9001_BIOS_BASE_ADDR 0x30
  63. #define WTK_VGA_PRESENT 0x300
  64. //
  65. // Weitek P9002 specific registers/definitions.
  66. //
  67. #define P9002_VGA_ID 0x30l
  68. #define OAK_VGA 1l
  69. #define TRIDENT_VGA 2l
  70. #define WTK_VGA 3l
  71. #define VGA_MSK 3l
  72. //
  73. // Viper PCI ID String to search for ROM BIOS.
  74. //
  75. #define VIPER_ID_STR "VIPER"
  76. #define BIOS_RANGE_LEN 0x8000
  77. //
  78. // Misc PCI definitions.
  79. //
  80. #define PCI_BIOS_ENB 0x01l // Bit def to enable the adapter BIOS
  81. #define PCI_BIOS_DIS ~PCI_BIOS_ENB // Bit def to disable the adapter BIOS
  82. #define P9001_IO_ENB 0x01 // Bit def to enable IO space
  83. #define P9001_MEM_ENB 0x02 // Bit def to enable mem space
  84. //
  85. // The following block defines the base address for each of the RS registers
  86. // defined in the Bt485 spec. The IO addresses given below are used to map
  87. // the DAC registers to a series of virtual addresses which are kept
  88. // in the device extension. OEMs should change these definitions as
  89. // appropriate for their implementation.
  90. //
  91. #define RS_0_PCI_9001_ADDR 0x03c8
  92. #define RS_1_PCI_9001_ADDR 0x03c9
  93. #define RS_2_PCI_9001_ADDR 0x03c6
  94. #define RS_3_PCI_9001_ADDR 0x03c7
  95. #define RS_4_PCI_9001_ADDR 0x0400
  96. #define RS_5_PCI_9001_ADDR 0x0401
  97. #define RS_6_PCI_9001_ADDR 0x0402
  98. #define RS_7_PCI_9001_ADDR 0x0403
  99. #define RS_8_PCI_9001_ADDR 0x0800
  100. #define RS_9_PCI_9001_ADDR 0x0801
  101. #define RS_A_PCI_9001_ADDR 0x0802
  102. #define RS_B_PCI_9001_ADDR 0x0803
  103. #define RS_C_PCI_9001_ADDR 0x0C00
  104. #define RS_D_PCI_9001_ADDR 0x0C01
  105. #define RS_E_PCI_9001_ADDR 0x0C02
  106. #define RS_F_PCI_9001_ADDR 0x0C03
  107. #define RS_0_PCI_9002_ADDR 0x03c8
  108. #define RS_1_PCI_9002_ADDR 0x03c9
  109. #define RS_2_PCI_9002_ADDR 0x03c6
  110. #define RS_3_PCI_9002_ADDR 0x03c7
  111. #define RS_4_PCI_9002_ADDR 0x0040
  112. #define RS_5_PCI_9002_ADDR 0x0041
  113. #define RS_6_PCI_9002_ADDR 0x0042
  114. #define RS_7_PCI_9002_ADDR 0x0043
  115. #define RS_8_PCI_9002_ADDR 0x0080
  116. #define RS_9_PCI_9002_ADDR 0x0081
  117. #define RS_A_PCI_9002_ADDR 0x0082
  118. #define RS_B_PCI_9002_ADDR 0x0083
  119. #define RS_C_PCI_9002_ADDR 0x00C0
  120. #define RS_D_PCI_9002_ADDR 0x00C1
  121. #define RS_E_PCI_9002_ADDR 0x00C2
  122. #define RS_F_PCI_9002_ADDR 0x00C3